Method for controlled erasing memory devices, in particular anal

Details Method for controlled erasing memory devices, in particular anal Method for controlled erasing memory devices, in particular anal

1999-01-21

2000-07-18

Mai, Son

Static information storage and retrieval

Floating gate

Particular biasing

36518524, 3651853, G11C 1604

Patent

active

060916427

ABSTRACT:
The controlled erase method includes supplying at least one erase pulse to cells of a memory array; comparing the threshold voltage of the erased cells with a low threshold value; selectively soft-programming the erased cells which have a threshold voltage lower than the low threshold value; and verifying whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.

REFERENCES:
patent: 5508959 (1996-04-01), Lee et al.
patent: 5568419 (1996-10-01), Atsumi et al.
patent: 5602789 (1997-02-01), Endoh et al.
patent: 5608672 (1997-03-01), Tang et al.
patent: 5636162 (1997-06-01), Coffman et al.
patent: 5642311 (1997-06-01), Cleveland et al.
patent: 5745410 (1998-04-01), Yiu et al.

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