Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Patent
1997-01-03
1999-06-01
Butler, Dennis M.
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
709 8, G06F 114
Patent
active
059084707
ABSTRACT:
A method for contention-free access and management of shared timers in a multiprocessing environment allocates at least two timers, which are used by all subject threads in a "ping-pong" manner. Each thread uses a local variable to determine which of the two timers to use for blocking. At initialization, the first timer tracks a first specified time duration and the second timer tracks a second specified time duration after the first specified time duration. When the first timer expires, it is reset by the master thread to expire at a third specified time duration after the second specified time duration. Similarly, when the second timer expires, it is reset by the master thread to expire at a fourth specified time duration after the third specified time duration. This process repeats itself, so that a timer is always active in the system. Following timer expiration, the non-master threads and the master thread perform processing tasks, and then block on a timer without contention or additional synchronization.
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Butler Dennis M.
NCR Corporation
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