Method for contemporaneous margin verification and memory...

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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C365S185200, C365S189070

Reexamination Certificate

active

07978501

ABSTRACT:
Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory cells. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory cells substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory cells may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).

REFERENCES:
patent: 6275417 (2001-08-01), Lee et al.
patent: 6282145 (2001-08-01), Tran et al.
patent: 7849712 (2010-12-01), Parkinson

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