Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-02
2001-04-17
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S783000
Reexamination Certificate
active
06218289
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for contact anneal in a semiconductor device and more particularly, relates to a method for contact anneal in a doped dielectric layer without the occurrence of dopant diffusion problems.
BACKGROUND OF THE INVENTION
In modem semiconductor devices built on a silicon substrate, P+ and N+ type doped regions in the silicon substrate are the basic elements of the device that must be connected in a specific configuration to form a desired circuit. The circuit must also be accessible to the outside world through conducting pads for testing and for bonding to metal pins in a packaged chip. In such a circuit, at least one low resistance metal layer must be deposited and patterned to form contacts and interconnects between the different regions on the chip. A variety of metal and metal alloys can be used for this purpose with aluminum as the most widely used contact and interconnect material due to its high conductivity, low cost, and compatibility with silicon.
In a typical metalization process, a wafer is first covered with an insulator layer, patterned and etched for contact openings in the insulator, and then metal such as aluminum is deposited and defined to form contact plugs and interconnecting leads. In modem sub-micron semiconductor technology, as the minimum feature size is reduced and the device dimensions continue to shrink, the reduced depth of a junction (i.e., a contact plug) results in an inevitable increase in the contact resistance of the junction. When an electrical contact is made between two dissimilar materials, a contact potential caused by a resistance typically develops at the interface between the two materials. The term contact resistance R
c
(in units of &OHgr;-cm
2
) defines the average resistance across the interface between two dissimilar materials that are in contact. While surface dopant concentration should be sufficiently high such that a sufficiently low contact resistance can be achieved in a sub-micron contact, the dopant concentration at the interface should be constant so that a reliable and consistent contact resistance can be determined.
The insulator material, in which the contact or interconnect is formed, is usually a dielectric material that has a dielectric constant that approaches unity. The dielectric layer is sometimes referred to as an inter-layer dielectric (ILD) or a poly-metal dielectric (PMD). A dielectric material can be deposited, planarized, and patterned to define openings for contacts to silicon and polysilicon. A typical dielectric composition suitable for forming contacts therein consists of a thick (i.e., 5,000~10,000 Å) film of silicate glass such as a phospho-silicate glass (PSG) or a boro-phospho-silicate glass (BPSG). These materials can be densified and reflowed at a temperature above their glass transition temperatures, for instance, at a temperature between about 700° C. and about 900° C. Dopant ions are typically added to silicate glass to reduce their reflow temperatures. For instance, PSG is normally doped with phosphine or trimethyphosphate, while BPSG is normally doped with trimethylborate. The reflow of the dielectric layer is necessary such that the glass material conformably covers steps, fills gaps between various device lines and achieves a more planar surface. For devices at more reduced dimensions, i.e., at the sub-0.5 micron level, the reflow process for the glass may not be adequate and instead, a chemical-mechanical polishing (CMP) method may be used.
In a contact opening formed in a doped silicate glass dielectric layer, the contact surface is highly susceptible to dopant contamination occurring at high temperatures such as that required to reflow the dielectric material. Contamination by dopant ions such as those of boron or phosphorus evaporated out of a BPSG dielectric layer can lead to an instability in contact resistance. Such instability in the contact resistance in turn leads to various reliability problems in the semiconductor device.
It is therefore an object of the present invention to provide a method for contact anneal in a doped dielectric layer that does not have the drawbacks and shortcomings of conventional contact annealing methods.
It is another object of the present invention to provide a method for contact anneal in a doped dielectric layer without the occurrence of a dopant diffusion problem and the resulting instability in the contact resistance.
It is a further object of the present invention to provide a method for contact anneal in a doped dielectric layer by providing a cap layer of oxide in the contact opening prior to the contact annealing step for blocking dopant ion diffusion.
It is still another object of the present invention to provide a method for annealing a contact in a doped dielectric layer by providing a cap layer of oxide that has a thickness sufficient to block dopant ion diffusion.
It is still another object of the present invention to provide a method for annealing a contact in a doped dielectric layer by providing a cap layer of oxide in the contact that is sufficiently thick capable of blocking dopant ion diffusion and yet is sufficiently thin so as not to impede the reflow of the dielectric layer in forming a contact opening having a rounded corner.
It is yet another object of the present invention to provide a method for contact anneal in a doped dielectric layer by providing a cap layer of oxide in the contact prior to the annealing step such that a rounded shoulder area in the contact opening is formed after the reflow process to facilitate a subsequent aluminum sputtering process.
SUMMARY OF THE INVENTION
The present invention provides a method for contact anneal in a doped dielectric layer without the occurrence of dopant diffusion problem by providing a cap layer of a dielectric material capable of stopping diffusion of dopant ions into the contact wherein the dielectric material layer is thick enough to stop dopant diffusion and yet thin enough to allow the reflow of the doped dielectric layer.
In a preferred embodiment, a method for annealing a contact in a doped dielectric layer can be carried out by first providing a semi-conducting substrate, forming a first dielectric layer on the substrate, depositing a second dielectric layer on the first dielectric layer where the second dielectric layer contains at least one type of dopant ion and is substantially thicker than the first dielectric layer, opening a contact in the first and the second dielectric layers, depositing a cap layer of a third dielectric material capable of stopping diffusion of dopant ions into the contact, and annealing the contact at a temperature sufficient to reflow the second dielectric layer. The thickness of the cap layer is between about 50 Å and about 600 Å, and preferably, between about 100 Å and about 300 Å. The doped dielectric layer is normally formed of a phospho-silicate glass (PSG) or a boro-phospho-silicate glass (BPSG) material that can be reflowed at a temperature between about 700° C. and about 900° C. The cap layer is preferably a plasma enhanced TEOS-ozone oxide material.
The present invention is also directed to an electronic structure that includes a semi-conducting substrate, a dielectric layer containing dopant ions and having a thickness sufficient for forming a contact, and an electrically conductive metal filling the contact wherein the contact was covered by a sacrificial oxide layer during a reflow process for the dielectric layer so as to prevent diffusion of dopant ions into the contact and the oxide layer was subsequently removed prior to the filling of the contact by a conducting metal.
REFERENCES:
patent: 5284800 (1994-02-01), Lien et al.
patent: 5492868 (1996-02-01), Lin et al.
patent: 5554565 (1996-09-01), Liaw et al.
patent: 08330252 (1996-12-01), None
K. D. Stonnington, et al “Synthesis and characterization of SiO2 films deposited using TEOS” J. Vac. Sci. & Tech. A, vol. 10, No. 4, pt. 1, p. 970-3, Jul., 1992.
Everhart Caridad
Tung & Associates
Vanguard International Semiconductor Corporation
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