Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1997-08-23
2002-07-09
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S761000, C438S778000, C438S785000
Reexamination Certificate
active
06417110
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly, to the construction of electrodes that must survive high temperature processing steps on silicon substrates.
BACKGROUND OF THE INVENTION
The present invention will be explained in the context of the construction of ferroelectric based capacitor-like structures; however, it will be apparent to those skilled in the art from the following discussion that the present invention may be applied to other integrated circuits. Ferroelectric based capacitors are in increasing demand as integrated circuit elements. Capacitors having lead lanthanum titanium zirconate (PLZT) dielectrics offer large dielectric constants which, in turn, make the construction of small capacitors with relatively large capacitances possible. A ferroelectric capacitor consists of a PLZT layer sandwiched between two planar electrodes. Capacitors utilizing platinum electrodes are particularly advantageous, since such capacitors provide a good crystallization platform with low leakage compared to capacitors utilizing other electrode materials.
Ferroelectric based field-effect transistors are also known to the art. These transistors have a structure which may be viewed as a capacitor in which the top electrode has been replaced by a semi-conductor layer having two separated contacts corresponding to the source and drain of the transistor. The bottom electrode and ferroelectric layer are constructed in essentially the same manner as the bottom electrode and ferroelectric layer of a ferroelectric capacitor.
An integrated circuit utilizing ferroelectric capacitor-like structures is typically constructed in two phases. First, the conventional CMOS circuits which connect to the ferroelectric devices are constructed in the silicon substrate. A protective layer of SiO
2
is then placed over the CMOS devices and the ferroelectric devices constructed on the protective layer or on a second protective layer deposited over the SiO
2
layer. The ferroelectric devices are connected to the underlying CMOS devices by etching vias in the protective layer.
The bottom electrode and ferroelectric layer of a ferroelectric structure are typically constructed by depositing a patterned bottom electrode on the protective layer and then covering the surface with the ferroelectric layer. The top electrodes are then deposited and the electrode/ferroelectric layer are stack etched back to the protective layer.
For example, U.S. Pat. No. 5,242,534 describes a construction method in which a titanium oxide layer is formed over the SiO
2
layer. A layer of titanium is deposited and the layer is masked and etched in those regions that are to become the bottom electrode leaving a trench in the titanium layer. The bottom electrode, typically platinum or a titanium/platinum stack, is then deposited in the trench. The mask is then removed and the exposed titanium is oxidized. This leaves the regions between the bottom electrodes covered with titanium oxide and the bottom electrode recessed in the titanium oxide layer. The PZT dielectric layer is then deposited over the wafer. The top electrodes are typically deposited as a uniform layer. The top electrodes and dielectric layer are then stack etched back to the titanium oxide layer in the regions between the capacitor-like structures.
The process described above subjects the bottom electrode structure to high temperatures during the annealing of the platinum structure and the subsequent sintering of the ferroelectric layer. The sintering of the ferroelectric layer typically involves subjecting the electrode structure to temperatures in excess of 650° C. These high temperature steps stress the bottom electrode/substrate attachment and lead to the bottom electrode being deformed or separated from the underlying substrate, thereby rendering the capacitor useless because of roughness, voids, hillocks (spikes).
Broadly, it is the object of the present invention to provide an improved method for constructing electrodes.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
SUMMARY OF THE INVENTION
The present invention is a method for constructing an electrode on a silicon substrate in which the electrode will be subjected to high temperatures during subsequent processing steps. A titanium oxide layer is deposited on the silicon substrate and annealed at a temperature higher than any subsequent temperature to which the titanium oxide layer will be subjected. The electrode is then deposited on the titanium oxide layer. The electrode is preferably platinum or a titanium/platinum composition. The platinum is also annealed to a temperature higher than any subsequent temperature to which the electrode will be subjected. In the preferred embodiment of the present invention, the electrode is constructed in a trench that is etched in a layer of metallic titanium that is deposited over the titanium oxide layer.
REFERENCES:
patent: 4759823 (1988-07-01), Asselanis et al.
patent: 4769686 (1988-09-01), Horiuchi et al.
patent: 5028455 (1991-07-01), Miller et al.
patent: 5242534 (1993-09-01), Bullington et al.
patent: 5338951 (1994-08-01), Argos, Jr. et al.
patent: 5443688 (1995-08-01), Toure et al.
R.D. Jones “Hybrid Circuit Design and Manufacture”, Marcek Dekker Inc, 1982, pp. 22-37, 1982.*
Jones, R.D. “Hybrid Circuit Desing and Manufacture”, Marcel Dekker Inc., 1982 p. iii.
Radiant Technologies INC
Utech Benjamin L.
Ward Calvin B.
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