Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-14
2007-08-14
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
11224156
ABSTRACT:
Integrated circuit devices having fixed and programmable logic portions are made by combining a hardware description language representation of the fixed logic and a hardware description language representation of the programmable logic to create a single hardware description language representation of a device. This allows multiple portions of programmable logic, distributed where needed in whatever size needed, to be interspersed among the fixed logic. Because the behavior of the programmable logic, rather than of the user programming, is being represented, a programmable logic architecture is provided that lacks behaviors, such as combinational loops, that would cause compilation of the hardware description language to generate errors.
REFERENCES:
patent: 5699283 (1997-12-01), Okazaki et al.
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5874834 (1999-02-01), New
patent: 6091262 (2000-07-01), New
patent: 6094065 (2000-07-01), Tavana et al.
patent: 6216257 (2001-04-01), Agrawal et al.
patent: 6242945 (2001-06-01), New
patent: 6490707 (2002-12-01), Baxter
patent: 6515509 (2003-02-01), Baxter
patent: 6526563 (2003-02-01), Baxter
patent: 6744274 (2004-06-01), Arnold et al.
patent: 6857110 (2005-02-01), Rupp et al.
patent: 6948105 (2005-09-01), Rajsuman
patent: 6961919 (2005-11-01), Douglass
patent: 2004/0015341 (2004-01-01), Ferris
patent: 2004/0162805 (2004-08-01), Wozniak
patent: 2005/0010378 (2005-01-01), Zeidman et al.
patent: 2005/0084076 (2005-04-01), Dhir et al.
patent: 2005/0149898 (2005-07-01), Hakewill et al.
patent: 2006/0015862 (2006-01-01), Odom et al.
patent: 2006/0195822 (2006-08-01), Beardslee et al.
patent: 2006/0259884 (2006-11-01), Fong et al.
Wilton, S.J.E., et al., “Programmable Logic IP Cores in SoC Design: Opportunities and Challenges”,Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, pp. 63-66 (May 2001).
Phillips, S., et al., “Automatic Layout of Domain-Specific Reconfigurable Subsystems for System-on-a-Chip”,Tenth ACM International Symposium on Field-Programmable Gate Arrays, pp. 165-173 (Feb. 2002).
Ghodrat, M., et al., “The Automatic FPGA Generator”,Proceedings of the 5th Annual International Computer Society of Iran Computer Conference, pp. 3-10 (2000).
Bozman Kimberly
Kafafi Noha
Wilton Steven J E
Wu James
Altera Corporation
Dinh Paul
Fish & Neave IP Group of Ropes & Gray LLP
Ingerman Jeffrey H.
Parihar Suchin
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