Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-03-27
2001-05-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06237129
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application relates to the following concurrently filed, commonly assigned U.S. patent application:
Ser. No. 09/049,892 invented by L. James Hwang, Eric F. Dellinger, Sujoy Mitra, Sundararajarao Mohan, Cameron D. Patterson, and Ralph D. Wittig, entitled “HETEROGENEOUS METHOD FOR DETERMINING MODULE PLACEMENT IN FPGAS”,
which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to Field Programmable Gate Arrays (FPGAs). More particularly, the invention relates to a method for constraining relative circuit element positions in structured FPGA layouts.
2. Description of the Background Art
Programmable ICs are a well-known type of digital integrated circuit that may be programmed by a user to perform specified logic functions. One type of programmable IC, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBS, IOBs, and interconnect structure are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
One such FPGA, the Xilinx XC4000™ Series FPGA, is described in detail in pages 4-5 through 4-78 of the Xilinx 1996 Data Book entitled “The Programmable Logic Data Book” (hereinafter referred to as “the Xilinx Data Book”), published September, 1996, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
As FPGA designs increase in complexity, they reach a point at which the designer cannot deal with the entire design at the gate level. Where once a typical FPGA design comprised perhaps 5,000 gates, FPGA designs with 20,000 gates are now common, and FPGAs supporting over 100,000 gates will soon be available. To deal with this complexity, circuits are typically partitioned into smaller circuits that are more easily handled. Often, these smaller circuits are divided into yet smaller circuits, imposing on the design a multi-level hierarchy of logical blocks.
Libraries of predeveloped blocks of logic have been developed that can be included in an FPGA design. Such library modules include, for example, adders, multipliers, filters, and other arithmetic and DSP functions from which complex designs can be readily constructed. The use of predeveloped logic blocks permits faster design cycles, by eliminating the redesign of duplicated circuits. Further, such blocks are typically well tested, thereby making it easier to develop a reliable complex design.
To offer the best possible performance, some library modules have a fixed size and shape, with relative location restrictions on each element. One type of module having a fixed size and shape is the Relationally Placed Macro (RPM) from Xilinx, Inc. RPMs are described in pages 4-96 and 4-97 of the “Libraries Guide” (hereinafter referred to as the “Xilinx Libraries Guide”), published October 1995 and available from Xilinx, Inc., which pages are incorporated herein by reference. An RPM is a schematic that includes constraints defining the order and structure of the underlying circuits. The location of each element within the RPM is defined relative to other elements in the RPM, regardless of the eventual placement of the RPM in the overall design. For example, an RPM might contain 8 flip-flops constrained to be placed into four CLBs in a vertical column. The column of four CLBs can then be placed anywhere in the FPGA.
Relative CLB locations in an RPM are specified using a Relative Location Constraint called “RLOC”. RLOC constraints are described in detail in pages 4-71 through 4-95 of the Xilinx Libraries Guide, which pages are incorporated herein by reference. Elements having an RLOC value of R0C0 are located in a given CLB corresponding to the (0,0) coordinate location. The next CLB “below” the (0,0) CLB is designated as R1C0, corresponding to the (0,1) coordinate location. When the FPGA design is mapped and placed (prior to the final routing step), these RLOC constraints are referenced and, in effect, make the RPM a “jigsaw puzzle piece” to be fitted into the FPGA along with other elements and/or modules. Although the RPM has a rigid size and shape, other logic can be placed within the borders of the RPM.
Although this coordinate-based method of specifying relative locations is a useful way to represent positions, modules including numerical coordinates can be difficult to maintain. When one element is added, moved, deleted, or resized, the coordinates of other elements (potentially all other elements in the module) can require modification. In addition, the coordinate values are affected by several other factors, such as the target FPGA architecture, the size of the target FPGA device, and the size of the module itself, which may in turn be affected by the results of the mapping phase of the map, place, and route process.
The CLB resources in different architectures may differ in both number and type. For example, the Xilinx XC4000 Series CLB includes two 4-input function generators, one 3-input function generator, and two flip-flops. The Xilinx XC3000™ Series CLB includes two 4-input function generators and two flip-flops. The Xilinx XC5200™ CLB includes four 4-input function generators and four flip-flops. Therefore, to re-target a module including numerically-specified relative coordinates from one of these architectures to another, considerable effort may be required.
Designs are typically entered either with schematic entry or Hardware Description Languages (HDLs). When schematic entry is used, explicit relative locations are typically given. When structural HDL code (e.g., structural VHDL) is used, the code can be parameterized and executed using the GENERATE statement. When the GENERATE statement is used, the assignment of RLOC coordinates to circuit elements in the VHDL code sometimes requires complicated arithmetic expressions, which can be a significant verification burden.
Although an RPM can be moved from place to place on an FPGA without modifying its relative coordinates, the processes of defining and modifying an RPM are subject to the limitations described above. It is therefore desirable to provide a method for constraining relative circuit element positions that does not use numerical coordinates. It is further desirable that the method be independent of the targeted FPGA architecture.
SUMMARY OF THE INVENTION
The invention supplies a method whereby placement information for elements of a logic module is specified in such a manner that specific coordinates need not be included. This method can be applied to any module or other element having an associated placement in a programmable device. Using the method of the invention, relative coordinates (such as the RLOC constraints discussed in relation to the prior art) need not be specified. Instead, the invention introduces a vector-based form of layout. Key words or phrases such as “COLUMN” or “ROW” indicate the manner in which the elements of the module are to be placed. Use of such parametric words or phrases removes from the module developer the burden of determining exactly how large the module will be for each parameter combination, and in some cases finding expressions by which the relative locations can be calculated.
REFERENCES:
patent: 4554625 (1985-11-01), Otten
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patent: 5208491 (1993-05-01), Ebeling et al.
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pat
Dellinger Eric F.
Hwang L. James
Mitra Sujoy
Mohan Sundararajarao
Patterson Cameron D.
Cartier Lois D.
Smith Matthew
Thompson Annette M.
Xilinx , Inc.
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