Method for conserving power by adjusting clock frequency based o

Details Method for conserving power by adjusting clock frequency based o Method for conserving power by adjusting clock frequency based o

1997-04-16

1999-09-07

Lee, Thomas C.

Electrical computers and digital processing systems: support

Computer power control

Power conservation

713330, 364550, 364556, 32420712, G06F 132

Patent

active

059481056

ABSTRACT:
Power saving methods for a battery powered electronic measurement system includes controlling the clock speed for different subsystems of the electronic measurement system and controlling the timing cycles of a controller of the electronic measurement system. Controlling the clock speed of the different subsystems includes using a controller clock for the controller and an internal clock for a signal generating and processing circuit. The internal clock runs at a high frequency during a measurement operation. During other times, the internal clock is disabled. The controller clock outputs a first clock signal having a slow frequency which is substantially slower than the internal clock signal and a second clock signal having an extremely slow frequency which is substantially slower than the first clock signal. Controlling the timing cycles of the controller includes operating the controller using a fast mode timing cycle when measurements are being made, a slow mode timing cycle when measurements are not being made, and a sleep mode timing cycle when the controller is in a sleep mode. Each of the timing cycles includes a different length halt portion. During a halt portion, all data processing by the controller is stopped and the controller is run using the second clock signal. In a fast portion of the fast mode timing cycle, the controller is run using the first clock signal. In slow portions of the other mode timing cycles, the controller is run using the second clock signal.

REFERENCES:
patent: 4974164 (1990-11-01), Lewis et al.
patent: 5023559 (1991-06-01), Andermo
patent: 5027428 (1991-06-01), Ishiguro et al.
patent: 5305452 (1994-04-01), Khan et al.
patent: 5317385 (1994-05-01), Silva et al.
patent: 5378935 (1995-01-01), Korhonen et al.
patent: 5440501 (1995-08-01), Shimomura et al.
patent: 5481697 (1996-01-01), Mathews et al.
patent: 5502689 (1996-03-01), Peterson et al.
patent: 5664201 (1997-09-01), Ikedea
patent: 5754867 (1998-05-01), Walker

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