Electrical computers and digital data processing systems: input/ – Intrasystem connection – System configuring
Reexamination Certificate
1999-06-07
2002-06-04
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
System configuring
C710S105000, C710S305000
Reexamination Certificate
active
06401151
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to bus architectures for computer systems. More specifically, the present invention relates to a bus architecture that can be configured through software control to selectively switch peripheral devices between different buses in order to improve system performance.
2. Related Art
Computer systems typically communicate with peripheral devices through a peripheral bus that is shared between a number of peripheral devices. This arrangement works well for the majority of peripheral devices, because most peripheral devices make limited use of the peripheral bus. However, as the performance of computer systems and peripheral devices continues to increase, some peripheral devices are beginning to encounter performance problems caused by contention between peripheral devices for access to the shared peripheral bus.
In order to overcome these performance limitations, some computer systems use a separate dedicated high-speed bus to communicate with a peripheral device requiring a large amount of capacity from a peripheral bus. For example, some computer systems have a separate bus for communicating with a graphics accelerator—such as the AGP bus found in many personal computer systems. This architecture works well for computer systems that require large amounts of bus capacity for a particular task, such a processing graphical images. However, this architecture is also inflexible because once the computer system is configured to provide bus capacity for a particular peripheral device, such as a graphics accelerator, it cannot be reconfigured for other tasks that require large amounts of bus capacity for other peripheral devices. For example, a computer system that is used as a file server may require large amounts of bus capacity for accesses to a disk subsystem, and a computer system that is used as a network server may require large amounts of bus capacity for a network subsystem.
What is needed is a computer system with a bus architecture that can selectively provide dedicated bus capacity to more than one peripheral device.
SUMMARY
One embodiment of the present invention provides a method for configuring a bus architecture under software control to selectively switch a plurality of peripheral devices between a plurality of buses. The method includes receiving bus configuration information in a configuration register. This configuration information specifies how peripheral devices are coupled to buses. If the configuration information specifies a first configuration, the system configures switching circuitry so that the first peripheral device communicates across the first bus and the second peripheral device communicates across the second bus. If the configuration information specifies a second configuration, the system configures the switching circuitry so that the first peripheral device communicates across the second bus and the second peripheral device communicates across the first bus.
In one embodiment of the present invention, the first bus is a shared bus coupled to more than one peripheral device and the second bus is a high-speed bus coupled to at most one peripheral device.
In one embodiment of the present invention, the system additionally tracks usage of the first peripheral device and the second peripheral device to determine which peripheral device is most active. Next, the system writes configuration information into the configuration register so that the most active peripheral device is coupled to the second bus.
In one embodiment of the present invention, the first peripheral device and the second peripheral device can include a video subsystem, a disk subsystem and a network subsystem.
REFERENCES:
patent: 5379384 (1995-01-01), Solomon
patent: 5887157 (1999-03-01), Klein et al.
patent: 5911149 (1999-06-01), Luan et al.
patent: 6094699 (2000-07-01), Surugucchi et al.
patent: 6148351 (2000-11-01), Takase
patent: 6173349 (2001-01-01), Qureshi et al.
patent: 6311245 (2001-10-01), Klein
Dharia Rupal
Micro)n Technology, Inc.
Park Vaughan & Fleming LLP
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