Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-12-27
2005-12-27
Padmanabran, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S129000, C711S161000
Reexamination Certificate
active
06981104
ABSTRACT:
A method for conducting checkpointing within a writeback cache having a cache memory with at least two memory banks. In one embodiment, a first pointer is set to indicate which cache entry of the at least two memory banks contains current data. A second pointer is set to indicate which cache entry of the at least two memory banks contains checkpoint data. Checkpointing is performed by selectively controlling said second pointer or said first pointer.
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Handy, “The Cache Memory Book”, 1998, Academic Press, 2nd ed, 51-56.
Baker Paul
Hewlett--Packard Development Company, L.P.
Lange Richard P.
Padmanabran Mano
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