Method for computing the sensitivity of a VLSI design to...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07487476

ABSTRACT:
A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.

REFERENCES:
patent: 6170078 (2001-01-01), Erle et al.
patent: 7024642 (2006-04-01), Hess et al.
patent: 7356787 (2008-04-01), Yan et al.
patent: 2006/0265684 (2006-11-01), Buehler et al.
patent: 2007/0294648 (2007-12-01), Allen et al.

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