Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization
Reexamination Certificate
2008-09-08
2011-10-18
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Optimization
C716S104000, C716S106000, C716S111000, C716S119000, C716S126000, C703S016000
Reexamination Certificate
active
08042085
ABSTRACT:
A technique and apparatus for reducing the complexity of optimizing the performance of a designed semiconductor circuit is disclosed. This technique of path compaction is used to reduce the time taken for optimization. The path compaction tool is used in design optimization to reduce the optimizer execution time. Compaction helps readability, usability and reduces synthesis and static timing analyzer (STA) runtime. The aim of path compaction is to reduce the number of constraints the optimizer has to go through during the optimization process. Path compaction has three dimensions. The first is to reduce number of “-through” elements in the constraint, thereby reducing the complexity of constraints developed The second is to combine the paths to reduce the number of constraints. The third is to combine the constraints to reduce the number of constraints to be checked and optimized. Path compaction is used when generating timing exception using timing exception tools.
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Bhatia Manish
Rahim Solaiman
Rejouan Housseine
Atrenta Inc.
Kik Phallaka
Sughrue & Mion, PLLC
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