Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-10-16
2004-07-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S772000, C714S767000
Reexamination Certificate
active
06760881
ABSTRACT:
BACKGROUND
The present invention relates generally to integrated circuit memory devices and, more particularly, to a method for combining a refresh operation with a parity check (and validation operation) in a DRAM-based content addressable memory (CAM).
A content addressable memory (CAM) is a storage device in which storage locations are identified by their contents, not by names or positions. A search argument is presented to the CAM and the location that matches the argument asserts a corresponding match line. One use for such a memory is in dynamically translating logical addresses to physical addresses in a virtual memory system. In this case, the logical address is the search argument and the physical address is produced as a result of the dynamic match line selecting the physical address from a storage location in a random access memory (RAM). CAMs are also frequently used for Internet address searching.
A conventional CAM includes an array of CAM cells, where each row of the CAM array corresponds to a stored word. The CAM cells in a row couple to a word line and a match line associated with the row. The word line connects to a control circuit that can either select the row for a read/write operation or bias the word line for a search. The match line carries a signal that, during a search, indicates whether the word stored in the row matches an applied input value. Each column of the conventional CAM array corresponds to the same bit position in all of the CAM words, while the CAM cells in a particular column are coupled to a pair of bit lines associated with the column. A search is applied to each pair of bit lines, which have a pair of complementary binary signals thereon that represent a bit of an input value. Each CAM cell changes the voltage on the associated match line if the CAM cell stores a bit that does not match the bit represented on the attached bit lines. Accordingly, if the voltage on a match line remains unchanged during a search, the word stored in that row of CAM cells matches the input word.
In a standard RAM, a parity check is typically performed during a normal read operation in order to detect “soft errors” that may occasionally occur during the storage or retrieval of binary information. A soft error may occur as a result of phenomena such as impacts of cosmic rays or alpha particles, wherein the value of a binary bit of stored data is changed. Generally speaking, a parity check is a technique in which a calculated parity bit associated with presently read data is compared with a previously stored parity bit that was generated during the original storage of a data word. A parity bit is the logical sum of all the data bits in a given word, and will either be “even” (i.e., “0”) or “odd” (i.e., “1”). A soft error is thus detected if the parity of the data word does not match the original parity stored in the parity memory cell.
However, in a conventional CAM design, a parity check operation is not readily performed in conjunction with a CAM match operation, since the data bits stored in the CAM cells are not explicitly “read” by the control circuitry. Rather, input data is applied to the CAM cells for comparison, thereby either triggering a match or not. Thus, in a conventional CAM device, a parity check is performed in conjunction with a read operation which is apart from the normal CAM search operation. Unfortunately, the time associated with performing an additional read operation (solely for the purpose of checking parity) limits the throughput of the CAM search capability. Moreover, if the parity check operation results in bad parity, than an additional write cycle is then used to invalidate any entry that fails the parity check.
BRIEF SUMMARY
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM). In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.
In one embodiment, the DRAM-based content addressable memory (CAM) is of a binary configuration. The invalidating of the data contained within the word includes setting a data valid bit to a data invalid state, the data valid bit being associated with the word. The data valid bit may be implemented within a DRAM storage cell, the DRAM storage cell being in addition to data storage cells used to store the data. Preferably, the data valid bit is implemented within an SRAM storage cell, the SRAM storage cell being in addition to data storage cells used to store the data.
In an preferred embodiment, the DRAM-based content addressable memory (CAM) is of a ternary configuration. The invalidating of the data contained within the word includes setting one of a plurality of data storage cells used to store the data to a forced mismatch state.
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Batson Kevin A.
Busch Robert E.
Chu Albert M.
Hall Ezra D. B.
Cantor & Colburn LLP
Capella Steven
De'cady Albert
International Business Machines - Corporation
Torres Joseph D.
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