Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2008-06-27
2010-02-16
Mai, Son L (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189050
Reexamination Certificate
active
07663950
ABSTRACT:
A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.
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Cernea Raul-Adrian
Moogat Farookh
Tsao Shou-Chang
Tseng Tai-Yuan
Davis , Wright, Tremaine, LLP
Mai Son L
Sandisk Corporation
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