Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2008-03-18
2008-03-18
Sarkar, Asok K. (Department: 2891)
Semiconductor device manufacturing: process
Chemical etching
C438S692000, C438S691000, C257SE21304
Reexamination Certificate
active
07344987
ABSTRACT:
The present invention relates to a method for performing chemical mechanical polishing. A high down-force step is performed. A low down-force step is performed. At least one of the down-force steps is modified, based on if one of the down-force steps exceeds an acceptable tolerance associated therewith. Other systems and methods are also disclosed.
REFERENCES:
patent: 5733177 (1998-03-01), Tsuchiya et al.
patent: 6113465 (2000-09-01), Kim et al.
patent: 6315645 (2001-11-01), Zhang et al.
patent: 6383928 (2002-05-01), Eissa
patent: 6551922 (2003-04-01), Grant et al.
patent: 6806193 (2004-10-01), Korthuis et al.
patent: 6913527 (2005-07-01), He
patent: 2002/0148997 (2002-10-01), Minamihaba et al.
patent: 2006/0211157 (2006-09-01), Smith et al.
patent: 2006/0228991 (2006-10-01), Kitajima et al.
“Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals”, Alvin L.S. Loke, and Tin Tin Wee, IEEE Solid State Circuits Society, Sep. 12, 2003, 21 pgs.
Doke Nilesh Shantaram
Leng Yaojian
Smith Stanley Monroe
Brady III W. James
Sarkar Asok K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Yevsikov Victor V.
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