Method for cmos latch-up improvement by mev billi (buried implan

Details Method for cmos latch-up improvement by mev billi (buried implan Method for cmos latch-up improvement by mev billi (buried implan

1997-03-19

1998-10-13

Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257374, 257375, 257376, 438228, 438526, 438529, H01L 2976, H01L 2994

Patent

active

058215891

ABSTRACT:
CMOS vertically modulated wells are constructed by using a blanket implant to form a blanket buried layer and then using clustered MeV ion implantation to form a structure having a buried implanted layer for lateral isolation in addition to said blanket buried layer.

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patent: 5160996 (1992-11-01), Odanaka
patent: 5292671 (1994-03-01), Odanaka
patent: 5384279 (1995-01-01), Stolmeijer et al.
patent: 5501993 (1996-03-01), Borland
Diffusion/Implantation, Dec. 1993, "MeV Implantation Technology Next-generation manufacturing with current-generation equipment" John Ogawa Borland, Ron Koelsch. brochure pp. 1-8.
Fowler, "MosFet Devices with high-gate dielectric integrity", IBM TDB, vol. 17, No. 1, Jun. 1974.

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