Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2005-02-22
2005-02-22
Wamsley, Patrick (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S095000
Reexamination Certificate
active
06859072
ABSTRACT:
Clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention do not include complementary logic elements. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. In addition, the clocked half-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic block to provide a driver function.
REFERENCES:
patent: 4247791 (1981-01-01), Rovell
patent: 5859548 (1999-01-01), Kong
patent: 6028454 (2000-02-01), Elmasry et al.
patent: 6211704 (2001-04-01), Kong
patent: 6373292 (2002-04-01), Choe
patent: 6496039 (2002-12-01), Choe
patent: 6614264 (2003-09-01), Choe et al.
patent: 6617882 (2003-09-01), Choe
patent: 6624664 (2003-09-01), Choe et al.
patent: 6630846 (2003-10-01), Choe
patent: 6639429 (2003-10-01), Choe
patent: 6661257 (2003-12-01), Choe
patent: 6703867 (2004-03-01), Choe et al.
patent: 6714059 (2004-03-01), Choe
patent: 6717438 (2004-04-01), Choe
Choe et al., “Dynamic Half Rail Differential Logic for Low Power”, IEEE 1997, pp. 1936 to 1939.
Jung et al., “Modular Charge Recycling Pass Transistor Logic (MCRPL)”, Electronics Letters, vol. 36 No.5, Mar. 2, 2000, pp. 406 to 405.
Kong et al., “Charge Recycyling Differential Logic for Low-Power Application”, ISSC96 secession 18, IEEE 0-780331962/98, pp. 302 to 448.
Choe et al., “Half Rail Differential Logic”, ISSCC97/Secession 25/Processors and Logic/Paper SP 25.6 IEEE 0-7803-3721-2/97, 1997, pp. 420 to 421, 336 to 337 and 489.
Won et al., “Modified Half Rail Differential Logic for Reduced Internal Logic Swing”, IEEE 0-7803-4455-3/98, 1998, pp. II-157 to II-160.
Kong et al., “Charge Recycling Differential Logic (CRDL) for Low-Power Application”IEEE Journal fo Solid-State Circuits, vol. 31, No. 9, Sep. 1996, pp. 1267 to 1276.
Gunnison McKay & Hodgson, L.L.P.
McKay Philip J.
Sun Microsystems Inc.
Wamsley Patrick
LandOfFree
Method for clock control of clocked half-rail differential... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for clock control of clocked half-rail differential..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for clock control of clocked half-rail differential... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3503597