Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-01-08
2008-01-08
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07318208
ABSTRACT:
The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive model. If this timing is not critical, the method uses a less accurate but less computationally intensive model. The method calculates a signal delay for each node from the drive strength, calculated capacitance and fan-out. This signal delay is compared to a design goal. This method achieves a better trade-off between timing determination run-time and accuracy. Timing criticality can be determined from one or more of conductor length/area, fan-out, logic depth and timing slack.
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Hill Anthony M.
Narasimha Usha
Savithri Nagaraj Narasimh
Brady W. James
Garbowski Leigh M.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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