Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-09-30
2001-02-27
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C355S043000, C382S276000, C345S420000, C345S424000
Reexamination Certificate
active
06195789
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to circuit design for semiconductor devices, and more particularly, to design methods for defining critical dimensions on a spherical semiconductor device.
Conventional integrated circuits, or “chips,” are formed from two-dimensional or flat surface semiconductor wafers. The semiconductor wafer is first manufactured in a semiconductor material manufacturing facility and is then provided to a fabrication facility. At the latter facility, several layers are processed onto the semiconductor wafer surface using various design concepts, such as VLSI design. Although the processed chip includes several layers fabricated thereon, the chip still remains relatively flat.
A fabrication facility is relatively expensive due to the enormous effort and expense required to create flat silicon wafers and chips. For example, manufacturing the wafers requires several high-precision steps including creating rod-form polycrystalline semiconductor material; precisely cutting ingots from the semiconductor rods; cleaning and drying the cut ingots; manufacturing a large single crystal from the ingots by melting them in a quartz crucible; grinding, etching, and cleaning the surface of the crystal; cutting, lapping, and polishing wafers from the crystal; and heat processing the wafers. Moreover, the wafers produced by the above processes typically have many defects which are largely attributable to the difficulty in making a single, highly pure crystal due to the above cutting, grinding, and cleaning processes as well as due to the impurities, including oxygen, associated with containers used in forming the crystals. These defects become more and more prevalent as the integrated circuits formed on these wafers become smaller.
Another major problem associated with modern fabrication facilities for flat chips is that they require extensive and expensive equipment. For example, dust-free clean rooms and temperature-controlled manufacturing and storage areas are necessary to prevent the wafers and chips from defecting and warping. Also, these types of fabrication facilities suffer from a relatively inefficient throughput as well as an inefficient use of the silicon. For example, facilities using in-batch manufacturing, where the wafers are processed by lots, must maintain huge inventories to efficiently utilize all the equipment of the facility. Also, because the wafers are round, and the completed chips are rectangular, the peripheral portion of each wafer cannot be used.
Still another problem associated with modern fabrication facilities is that they do not produce chips that are ready to use. Instead, there are many additional steps that must be completed, including cutting and separating the chip from the wafer; assembling the chip to a lead frame, which includes wire bonding, plastic or ceramic molding, and cutting and forming the leads; positioning the assembled chip onto a printed circuit board; and mounting the assembled chip to the printed circuit board. The cutting and assembly steps introduce many errors and defects due to the precise requirements of such operations. Additionally, the positioning and mounting steps are naturally two-dimensional in character and, therefore, do not support curved or three-dimensional areas.
There are numerous problems associated with applying a two-dimensional circuit design to a three-dimensional object, such as a sphere. Specifically, VLSI circuit designs for flat chips are achieved by using two-dimensional based computer aided circuit design tools. However, these conventional methods of VLSI circuit design are not suitable for three-dimensional surfaces because modifying a two-dimensional design to fit onto a three-dimensional curved surface results in two problems. First, a two-dimensional design element, such as a line or shape, is deformed when fitted over a three-dimensional curved surface. This deformation results in distortion of the circuit design, which results in unacceptable circuit elements. Second, in two-dimensional circuit VLSI design, square and/or rectangular design units are used to modularize the design for ready transformation onto a two-dimensional surface. However, these conventional units do not fit properly onto a curved surface, such as a sphere. As a result, the distribution of the units on the surface of the sphere results in random and inefficient use of the sphere's surface area. Furthermore, the designer can not easily navigate over the surface of the sphere to determine location, direction, and space or surface area remaining.
Another problem with designing on the three-dimensional curved surface relates to designing circuits that have regions with critical dimensions enclosed by parallel or perpendicular boundary lines. For example, in order to ensure the proper performance of a semiconductor gate device, a constant gate width is essential. A gate typically has an active region with parallel boundaries and a constant width across the active region. When mapping a two-dimensional circuit design onto the three-dimensional surface, certain lines that must be kept parallel are distorted by this process. Distortion of the parallel lines results in distortion of the gate region and variations in the width of the active region. This in turn changes the characteristics and performance of the device.
Therefore, what is needed is a method for implementing a circuit design on a three-dimensional surface, such as a spherical semiconductor device, without distortion of critical dimensions.
SUMMARY OF THE INVENTION
The present invention, accordingly, provides a method for generating parallel and perpendicular lines without distortion of critical dimensions. To this end, the method for designing an integrated circuit on the surface of a spherical semiconductor device includes the steps of designing a circuit utilizing a great-circle-small-circle framework to define parallel or perpendicular lines.
One advantage of the present invention is that it results in an ability to generate a framework of parallel and perpendicular lines whereby a variety of circuits can be mapped from conventional two-dimensional circuit designs onto three-dimensional surfaces. A corresponding grid system on the sphere can be generated by combining great circle and small circles that are parallel or perpendicular to the great circle.
Another advantage of the present invention is that it allows IC designers to start their design at any point on the sphere and expand in any direction.
Another advantage of using the great-circle small-circle framework is that designers can define the orientation of a great circle without any restriction. Designers can also arrange a circuit design in any direction because a fixed grid system with unit shapes are not a limitation of the great-circle-small-circle framework.
DEFINITIONS
SPHERE: A set of points in space having equal distance to a center point. A sphere is a surface and not a solid body, although it may enclose a solid body.
GREAT CIRCLE: The section of a sphere made by a plane passing through the center of the sphere is called a great circle of the sphere.
SMALL CIRCLE: The section of a sphere made by a plane which does not pass through the center of the sphere is called a small circle of the sphere.
MINOR ARC: Two points lying along either a great circle or a small circle divide either the great circle or the small circle into two arcs, the smaller of which is called the minor arc of the points.
GREAT-CIRCLE-SMALL-CIRCLE FRAMEWORK: A framework utilizing at least one great circle and one small circle in parallel or perpendicular alignment.
SURFACE DISTANCE: The length of a minor arc of a great circle that is perpendicular to two parallel lines.
CRITICAL DIMENSIONS: Any geometrical distance in a circuit that has a special dimensional requirement and spacial separation for its boundaries.
REFERENCES:
patent: 5361385 (1994-11-01), Bakalash
patent: 5367465 (1994-11-01), Tazawa et al.
patent: 5416729 (1995-05-01), Leon et al.
patent: 5461455 (1995-10-01), Coteus et a
Ball Semiconductor Inc.
Haynes and Boone LLP
Smith Matthew
Speight Jibreel
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