Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-04-15
2008-04-15
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10946925
ABSTRACT:
A method, algorithm, software, architecture and/or system for placing circuit blocks and/or routing wires in a circuit design is disclosed. In one embodiment, a method of placing can include: (i) determining a first signal path between first and second circuit blocks and determining a second signal path between first and third circuit blocks; and (iii) placing the first circuit block relative to the second and third circuit blocks in a position related to a switching activity of the first and second signal paths. The circuit blocks can include standard cells configured to implement a logic function, other components, or integrated circuits, for example. The switching activity can include a switching frequency determination based on simulation results of the first and second signal paths between the circuit blocks. Embodiments of the present invention can advantageously reduce power consumption as well as supply noise by optimally placing circuit blocks in an automated place-and-route flow. Further, signal integrity problems due to non-optimal circuit block or component placement can be minimized.
REFERENCES:
patent: 6230304 (2001-05-01), Groeneveld et al.
patent: 6253361 (2001-06-01), Buch
patent: 6321183 (2001-11-01), Tatsumi
patent: 6453446 (2002-09-01), Van Ginneken
patent: 6496965 (2002-12-01), Van Ginneken et al.
patent: 6507941 (2003-01-01), Leung et al.
patent: 6530065 (2003-03-01), McDonald et al.
patent: 6553338 (2003-04-01), Buch et al.
patent: 6662348 (2003-12-01), Naylor et al.
patent: 6725438 (2004-04-01), Van Ginneken
patent: 6950998 (2005-09-01), Tuan
patent: 7062425 (2006-06-01), Bell et al.
patent: 2004/0015803 (2004-01-01), Huang et al.
patent: 2004/0049747 (2004-03-01), Yamasaki et al.
patent: 2004/0073878 (2004-04-01), Hasegawa et al.
patent: 2004/0150422 (2004-08-01), Wong
patent: 2004/0199883 (2004-10-01), Palumbo
patent: 2005/0034091 (2005-02-01), Harn
patent: 2006/0031795 (2006-02-01), Rahmat et al.
Jim Flynn and Brandon Waldo; Power Management in Complex SoC Design (16 Pages); Apr. 2004; Synopsis, Inc., 700 East Middlefield Rd., Mountain View, CA 94043; http://www.synopsys.com/sps.
Astro-Rail: A Comprehensive Power-Integrity Analysis, Implementation and Verfication Tool (2 Pages); Data Sheet, May 2003; Synopsis, Inc., 700 East Middlefield Rd., Mountain View, CA 94043.
Burstein Michael
Komorov Mikhail
Sergeev Georgy
Dinh Paul
Fortney Andrew D.
Golden Gate Technology, Inc.
Memula Suresh
Plumb Alec B.
LandOfFree
Method for circuit block placement and circuit block... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for circuit block placement and circuit block..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for circuit block placement and circuit block... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3922074