Abrading – Precision device or process - or with condition responsive... – With indicating
Reexamination Certificate
2000-07-13
2002-08-06
Eley, Timothy V. (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
With indicating
C451S036000, C451S041000
Reexamination Certificate
active
06428387
ABSTRACT:
CROSS-REFERENCE TO RELATED PATENT/PATENT APPLICATIONS
The following commonly assigned patent/patent applications are hereby incorporated herein by reference:
Patent No./Ser. No.
Filing Date
TI Case No.
09/034,514
03/04/98
TI-23590AA
FIELD OF THE INVENTION
The present invention relates to an chemical mechanical polishing method using a high selective slurry. Specifically, the invention involves using a modified slurry formed by mixing a polishing slurry with a salt of tetramethyl ammonium and hydrogen peroxide with a chemical mechanical polishing method.
BACKGROUND OF THE INVENTION
Various isolation structures are presently used for fabricating semiconductor devices. For example, shallow isolation structures are used in order to isolate adjacent electronic devices (such as transistors) which are formed in fabricating certain semiconductor circuits. Typically, such shallow isolation structures are created using the well-known LOCal Oxidation of Silicon (LOCOS) isolation technique. In the LOCOS process, a pad-oxide (SiO
2
) layer is first grown on the surface of a semiconductor substrate with a silicon nitride (Si
3
N
4
) layer being deposited over the pad-oxide layer. Using well-known photolithography methods, these layers are then patterned to define the width of the shallow recess to be etched in the substrate. Once the shallow recess has been etched, the substrate is subjected to an oxidation process where silicon dioxide (SiO
2
) is grown in the recess; the silicon nitride layer which has not yet been removed prevents any oxide growth over the surface of the substrate. As a result, oxide grows to fill the entire recess including the opening in the patterned oxide and silicon nitride layers which defined the width of the shallow recess. The disadvantages to this process is that the silicon dioxide formed in the recessed opening is grown in an isotropic manner, which consumes surface area on the semiconductor circuit. This causes the adjacent electronic devices that are being separated to be a fixed minimum distance apart.
Another technique used to create transistor isolation structures is by using a trench formed in the substrate. This method is known as Shallow Trench Isolation (STI). In the STI process, a pad-oxide (SiO
2
) layer is grown on the semiconductor substrate and a silicon nitride (Si
3
N
4
) layer formed on the pad-oxide layer. Using well known methods the Si
3
N
4
layer is patterned and etched to define the widths of the isolation structures. The semiconductor substrate is etched to form trenches and silicon oxide is used to fill the trenches and cover the semiconductor surface. Using well known methods, the silicon oxide is patterned and etched before using chemical mechanical polishing (CMP) to remove the silicon oxide covering the silicon nitride layer. The patterning and etching of the silicon oxide before CMP is necessary to reduce dishing of the silicon oxide film in the trenches. Following the removal of the silicon oxide layer, the silicon nitride layer is removed and electronic devices can be fabricated on the semiconductor substrate.
The major disadvantage of the above described STI methodology is the pattern and etch process steps required before removal of the silicon oxide using CMP. The silicon oxide layer is patterned using potolithography which adds cost to the process. In addition, portions of the silicon oxide film remaining after the pattern and etch processes can break off during CMP scratching the semiconductor surface.
The removal of the silicon oxide layer using CMP is accomplished through the use of an abrasive slurry. In general, the CMP process is accomplished by bringing a wafer mounted on a rotating carrier into contact with a rotating polishing pad upon which the slurry is delivered. CMP is a combination of mechanical polishing and the chemical action of the slurry. In general, the slurry used in this process has a selectivity of <5:1, silicon oxide polish rate to silicon nitride polish rate. It is this low slurry selectivity that necessitates the patterning and etching of the silicon oxide layer before polishing.
Various methods have been tried to reduce the dishing problem. Boyd and Ellul (J. M. Boyd, et al., Electochem. Soc. Proc., Vol. 95-5, 1996, p. 290) reported the use of a thin nitride over coat deposited on top of the gap filled oxide to reduce dishing. The nitride overcoat provides protection to the underlying oxide in low lying regions while the high level oxide is being polished at a much faster rate due to the oxide:nitride selectivity of 4:1.
SUMMARY OF INVENTION
The instant invention is a CMP method using a high selective slurry. The method comprises: delivering a modified slurry to a surface of a polishing pad, said pad being affixed to a rotating platen, wherein said modified slurry consists of combining a slurry with salt of tetramethyl ammonium and hydrogen peroxide; attaching a semiconductor wafer with a downwardly facing surface to a rotating wafer carrier; and bringing said downwardly facing semiconductor wafer surface into contact with said surface of said polishing pad.
Advantages of the instant invention include high planarization rates with wafer range capability of less than 500A, point of use mixing of high pH chemicals, and accurate end point determination. Other technical advantages will be readily apparent to one skilled in the art from the following FIGUREs, description, and claims.
REFERENCES:
patent: 5938505 (1999-08-01), Morrison et al.
patent: 6140245 (2000-10-01), Lee
patent: 6179688 (2001-01-01), Beckage et al.
Hunt Kyle P.
Morrison William R.
Brady III W. James
Eley Timothy V.
McLarty Peter K.
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