Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-03-27
2007-03-27
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S010000, C714S055000
Reexamination Certificate
active
10393550
ABSTRACT:
A method for checking the reset function of an embedded processor is described. First, a check is made to see if a reset “flag” is not set (202) before branching to execute the test routine that initiates the embedded processor's reset (206). The test program sets the flag (204) before initiating the reset. When the processor resets and executes the test program from the beginning again, it determines that the flag was set (202), and it does not execute the reset instructions again.
REFERENCES:
patent: 6014758 (2000-01-01), Poisner
patent: 6438709 (2002-08-01), Poisner
patent: 1094382 (2001-04-01), None
“Register” “FPGA” Microsoft Computer Dicitonary (c) 2002. Microsoft Press.
IBM, “PowerPC Embedded Processors Apllication Note”; “PowerPC 40x Watch Dog Timer”; Jul. 7, 1998, Version 1.0; IBM Microelectronics Research Triangle Park; downloaded from http://www-3.ibm.com/chips/techlib/techlib.nsf/products/PowerPC—405CR—Embedded—Processor; pp. 1-13.
Beausoliel Robert
Brush Robert
Hernandez Peter
Urick Matthew
LandOfFree
Method for checking the reset function in an embedded processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for checking the reset function in an embedded processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for checking the reset function in an embedded processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3771052