Method for checking the integrity of a clock tree

Details Method for checking the integrity of a clock tree Method for checking the integrity of a clock tree

2008-01-28

2009-12-08

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S003000, C327S007000, C327S142000, C327S143000, C327S144000

Reexamination Certificate

active

07629818

ABSTRACT:
A method and device detect synchronization errors between logic signals of a group of logic signals. A control word is loaded into a shift register arranged in loop and clocked by resulting logic signals equal to the result of the OR logic function and to the result of the AND logic function applied to the logic signals of the group of logic signals. The value of the control word is monitored as it propagates in the shift register, and a synchronization error signal is sent if the control word changes value. Application in particular for checking the integrity of a clock tree in an integrated circuit.

REFERENCES:
patent: 5309111 (1994-05-01), McNeely et al.
patent: 5498983 (1996-03-01), Schoellkopf
patent: 6556057 (2003-04-01), McClure
Fluker et al., “High Resolution Skew Measurement,” Wescon Conference Record, Nov. 17-19, 1992, North Hollywood, California, pp. 15-20.

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