Optics: measuring and testing – By polarized light examination – With light attenuation
Patent
1990-08-13
1991-09-03
Evans, F. L.
Optics: measuring and testing
By polarized light examination
With light attenuation
324158R, 355 55, 355 77, 356401, 430 30, G01B 1100, G03C 500, G03B 2732
Patent
active
050447505
ABSTRACT:
A method for measuring the proper exposure and registration of layers of desired circuit features on an integrated circuit wafer. The process of making the integrated circuit feature is modified in three ways. First, a structure is added to the mask pattern for each layer, apart from the desired circuit feature and parallel with and abutting the previous layer structure, comprising a plurality of geometric patterns arranged in a progressively overlapping edge-to-edge orientation on the mask pattern. The progressive overlap is such that at one end of the structure there is a substantial separation between the opposing edges of the geometric patterns, in the middle of the structure the opposing edges of the geometric patterns meet, and at the other end of the structure there is a substantial overlap of the opposing edges of the geometric patterns. The non-opposing edges of the geometric patterns are offset relative to a reference pattern in the middle of the structure. Second, the degree of exposure of the structure on a photoresist layer is analyzed. The proper degree of exposure is obtained when the opposing edges of each geometric pattern meet in the middle of the structure, an underexposed or overexposed condition exists when the point at which the opposing edges meet has shifted from the middle of the structure. Third, the registration of succeeding layers of features is analyzed. Proper registration is obtained when the abutting, non-opposing edges of the parallel structures of each layer meet at the reference pattern.
REFERENCES:
patent: 3974443 (1976-08-01), Thomas
patent: 4200396 (1980-04-01), Kleinknecht et al.
patent: 4347479 (1982-08-01), Cullet
patent: 4399205 (1983-08-01), Bergendahl
patent: 4566192 (1986-01-01), Hankins et al.
patent: 4639142 (1987-01-01), Chow et al.
patent: 4672314 (1987-06-01), Kokkas
patent: 4717445 (1988-01-01), Leung
patent: 4806457 (1989-02-01), Yanagisawa
patent: 4908656 (1990-03-01), Suwa et al.
patent: 4963924 (1990-10-01), Gill et al.
Murray, "Measuring Dimensions Using Murray Dagger", Semiconductor International, Dec. 1982.
Evans F. L.
National Semiconductor Corporation
LandOfFree
Method for checking lithography critical dimensions does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for checking lithography critical dimensions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for checking lithography critical dimensions will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1003773