Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2003-02-18
2004-12-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06834377
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for checking an integrated electrical circuit, which is in the form of a layout on a computer system, for faults caused by the manufacturing process or by the configuration of the integrated electrical circuit.
Checks such as these frequently make use of methods in which integrated electrical circuits are checked using proprietary manufacturer-specific design rule check rules or DRC rules. Furthermore, methods are feasible, in particular, test programs for detecting high-impedance circuit elements that cause faults and are connected to a number of circuit networks. These methods check the integrated electrical circuits for faulty circuit elements on a computer system by inserting “soft connects.”
Methods such as these for checking integrated electrical circuits are dependent on the availability of a description that is as realistic as possible of the integrated electrical circuit to be checked, on a memory unit in a computer system, with this description being created such that conventional test procedures can be applied to the description.
Integrated electrical circuits are subdivided into a large number of electrical circuit networks that are connected to one another. The characteristics of these circuit networks are frequently stored in the form of polygon data structures in order to create a layout of the integrated electrical circuit, with these polygon data structures using polygons to represent the circuit configurations contained in the respective circuit network.
In such a case, a separate polygon data structure is produced for each circuit network, with information from a number of circuit networks, which match electrically and geometrically, in each case being combined to form a polygon data structure. In reality, integrated electrical circuits often contain different electrical circuit networks, which have the same electrical characteristics, or electrical characteristics that are very similar to one another, but in which the geometry of the circuit elements that they contain differs. Separate polygon data structures are frequently produced in each case for circuit networks such as these when creating a description of an integrated electrical circuit on a computer system.
When producing a large number of polygon data structures that are very similar to one another, one problem that arises is that a very large memory area is required to describe the basic integrated electrical circuit on a memory unit of a computer system. A further disadvantage in this case is that the formation of the data structure of the circuit description from the individual polygon data structures is highly time-consuming. Furthermore, the memory requirement and the time required for use of the test procedures described above for a circuit description such as this are very extensive. These disadvantages become even more important as the integrated electric circuits on which they are based becomes more extensive and more complex.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for checking an integrated electrical circuit that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that can be used to create an improved description of an integrated electrical circuit. The integrated electrical circuit is intended to be capable of being checked for faults quickly and reliably, using this description.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for checking an integrated electrical circuit to be described by a layout including circuit network descriptions of the integrated electrical circuit, each of the circuit network descriptions being in a form of one of a file and a part of a file on a memory unit of a computer system and each of the circuit network descriptions having at least one polygon each representing one circuit element of the integrated electrical circuit and information regarding electrical characteristics of circuit elements of the integrated electrical circuit, the layout having instantiations of at least one circuit network description and information about a geometrical shape and a configuration of the instantiations with respect to one another, the layout being described by a raw data structure associating each instantiation of a circuit network description with only one polygon data structure, includes the step of carrying out with a computer program the steps of (a) selecting a circuit network description from the layout, (b) determining the instantiations of the circuit network description in the layout, (c) determining the respectively geometrically identical and geometrically different instantiations of the circuit network descriptions by analyzing polygon data structures, (d) forming variants for the instantiations of the circuit network descriptions and assigning the instantiations to these variants, geometrically different instantiations being combined into respectively different variants and geometrically matching instantiations being combined into respectively identical variants, (e) forming a new data structure associating the circuit network description with only one polygon data structure, geometrical differences between the instantiations of the same circuit network description being taken into account by variants in the polygon data structure, (f) storing the formed new data structure as one of a file and a part of a file on the memory unit of the computer system, and (g) checking the layout of the integrated electrical circuit using the new data structure stored in step f) for faults caused by a configuration of the integrated electrical circuit.
With the objects of the invention in view, there is also provided a method for checking an integrated electrical circuit to be described by a layout including circuit network descriptions of the integrated electrical circuit, each of the circuit network descriptions being in a form of one of a file and a part of a file on a memory unit of a computer system and each of the circuit network descriptions having at least one polygon each representing one circuit element of the integrated electrical circuit and information regarding electrical characteristics of circuit elements of the integrated electrical circuit, the layout having instantiations of at least one circuit network description and information about a geometrical shape and a configuration of the instantiations with respect to one another, the layout being extending over a number of levels disposed one above another, the layout being described by a raw data structure associating each instantiation of a circuit network description with only one polygon data structure, includes the step of carrying out with a computer program the steps of (a) selecting a circuit network description from the layout, (b1) selecting a highest level from the layout, (b2) determining the instantiations of the selected circuit network description on the level selected in step b1), (b3) forming difference polygons by comparing the instantiations on the level selected in step b1) in pairs, (b4) forming variants for instantiations having different difference polygons, (b5) checking the difference polygons acting on circuit network descriptions in a next-lower level, (b6) assigning the instantiations to the variants formed in step b4) based upon the difference polygons, (c1) selecting the next-lower level, (c2) determining the instantiations of the selected circuit network description on the level selected in step c1), (c3) forming difference polygons by comparing the instantiations on the level selected in step c1) in pairs, (c4) combining the difference polygons formed in step c3) with the previously formed difference polygons, (c5) checking the difference polygons acting on circuit network descriptions in a next-lower level, (c6) assigning the instantiations to the variants already having been formed based upon the difference polygons, (
Baader Peter
Ludwig Burkhard
Greenberg Laurence A.
Infineon - Technologies AG
Levin Naum
Mayback Gregory L.
Siek Vuthe
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