Method for checking an IC layout

Details Method for checking an IC layout Method for checking an IC layout

2006-11-07

2006-11-07

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07134108

ABSTRACT:
A method for checking an IC layout is used for checking the wire line width in the circuit layout. The IC includes at least a first metal layer having at least a wire, and the wire has a plurality of wire segments. The method includes the steps of checking the width of each wire segment, wherein if at least a narrow wire segment has a width smaller than a predetermined width, the narrow wire segment is removed; if there is at least a non-coupling wire segment not coupled to a voltage source in the remained wire segments, outputting the non-coupling wire and disposing a coupling wire to couple the non-coupling wire segment and the voltage source.

REFERENCES:
patent: 5349542 (1994-09-01), Brasen et al.
patent: 5367467 (1994-11-01), Sezaki et al.
patent: 5537328 (1996-07-01), Ito
patent: 5831867 (1998-11-01), Aji et al.
patent: 6109775 (2000-08-01), Tripathi et al.
patent: 6405346 (2002-06-01), Nawa
patent: 2001/0008312 (2001-07-01), Yamada et al.
patent: 2002/0024148 (2002-02-01), Itoh

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