Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-07-23
2002-04-02
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S210130
Reexamination Certificate
active
06366511
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for checking a semiconductor memory device which is constructed in integrated form on a semiconductor chip, with a plurality of memory cells disposed on a semiconductor substrate, each for one binary information value, data lines for reading out and writing in information values, gate transistors associated with the memory cells for selectively clearing a data path between a given memory cell and a data line, selection lines for purposefully triggering the gate transistors, and at least one in-chip reference voltage which is adjusted to a predetermined normal value when the semiconductor memory device is functioning as intended.
With increasing complexity and memory depth of a semiconductor memory device constructed in integrated form on a semiconductor chip, especially in the case of a dynamic random access memory device (a so-called DRAM), the test methods, or test programs if a computer is used, to be carried out for testing the functional capability of the semiconductor memory device, preferably before the semiconductor chip is encapsulated in a housing, become more and more extensive, and the time taken by the individual tests becomes longer and longer, so that performing the tests requires ever greater effort. The goal of such a method or test program is not only to check the memory chip for its basic functional capability with adequate margins, but also especially to track down defective or weak memory cells so that they can be replaced, optionally by using redundant cells that are also present on the chip.
Integrated semiconductor memory devices, especially those of the one-transistor memory cell type, are vulnerable to so-called soft errors, that is alpha rays that typically originate in the component housing being used. Experiments have shown that the semiconductor memory circuits react variously markedly to those alpha rays, depending on whether an information value was supposed to be stored as a physical zero or a physical one (a physical zero can correspond to a logical 0 value, but can also correspond to a logical 1 value, with the association being dependent on the particular circuitry chosen). It has been found that that is the consequence of a so-called weighting asymmetry in the reading amplifier, so that a stored datum of physical zero cannot be read out with the same certainty and safety margin as a stored datum of physical one, and vice versa. Thus the danger of soft errors increases with respect to the one type of datum, while it decreases for the other type of datum. Therefore, depending on the types of data, it is also complicated to detect defective or weak memory cells.
It is not yet possible with conventional test programs to detect and reject all of the memory cells that for process reasons (being particle-induced, for instance) furnish a poor reading signal, yet such cells represent a potential risk to the customer because under special conditions they can still cause failure. That directly worsens the quality of the products being furnished. In order to solve that problem, the methods and test programs used thus far for checking a semiconductor memory device have been made longer and more precise. However, on one hand, such extensive test programs require a considerable expenditure of time for complete checking of a semiconductor memory device, while on the other hand, it has been found that at least sometimes, the attainable rejection rate, even with extensive test programs, is not especially high or adequate.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a simple method for checking a semiconductor memory device constructed in integrated form on a semiconductor chip, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type, which can be carried out without major expenditure of time or labor and which enables the most complete possible detection and rejection of defective or weak memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for checking a semiconductor memory device integrated on a semiconductor chip, which comprises providing the semiconductor memory device with a plurality of memory cells each being disposed on a semiconductor substrate for one binary information value, data lines for reading out and writing in information values, gate transistors being associated with the memory cells for selectively clearing a data path between a given memory cell and a data line, selection lines for purposefully triggering the gate transistors, and at least one in-chip reference voltage being adjusted to a predetermined normal value when the semiconductor memory device is functioning as intended, and carrying out the method for checking the semiconductor memory device integrated on a semiconductor chip by at least intermittently varying the at least one in-chip reference voltage, and detecting and weighting the information values read out at the at least intermittently varied reference voltage.
In accordance with another mode of the invention, the in-chip reference voltage is thus lowered during some tests and raised during some tests. In this way, when the in-chip reference voltage is lowered, the reading signal of physical zeros decreases, or if the reference voltage is raised the reading signal of physical ones increases, so that memory cells which have reduced loading capacity or other defects furnish a reading signal that is too small for reliable weighting, and they can therefore be detected as weak or defective memory cells in a simple way and can optionally replaced by redundant cells.
In accordance with a further mode of the invention, in order to carry out the method of the invention, it is necessary that the in-chip reference voltage be varied temporarily or permanently from outside (increased or decreased as compared with the predetermined normal value) and/or adjusted.
In accordance with an added mode of the invention, this can be done either by impressing or programming the in-chip reference voltage from outside at a suitable terminal pad, or through so-called fuses (light fuses, laser fuses, electrical fuses or the like), which are constructed as irreversible switches on the chip in the form of redundant line connections that can be severed as needed, or within a test mode. In each case, through the use of a relatively simply accomplished variation of the in-chip reference voltage, a method for checking defective cells that is faster than previously known testing methods can be carried out with an adequately high rejection rate.
In accordance with a concomitant mode of the invention, the in-chip reference voltage is the supply voltage VDC of so-called dummy memory cells. In integrated semiconductor circuits, it is generally usual, before data are read out of the memory cells, to precharge the bit lines to a bit line potential VBL (generally known as a precharge operation or as charging with a precharge potential). This serves to effectively supply the reading amplifiers, which are generally flip-flop circuits that function differentially, after the readout for weighting and amplification of the reading signals, with only these reading signals, since the bit line potential VBL is present at both inputs of the reading amplifiers with the same value and thus is not taken into account by the differentially functioning reading amplifiers. Typically, a value is applied as the bit line potential VBL that corresponds to half the difference between the supply voltage potential VDD and the ground potential VCC. In semiconductor memory circuits that function internally of the circuit with a so-called internal supply voltage potential VDDint which is lowered, as compared with the supply potential present in the finished component, the corresponding half-difference between this internal supply voltage potential VDDint and the ground potential VSS is applied. If the semiconductor memory circuit also has the afore
Der Ropp Thomas Von
Rieger Johann
Infineon Technologies
Zarabian A.
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