Method for characterizing interconnect timing characteristics

Details Method for characterizing interconnect timing characteristics Method for characterizing interconnect timing characteristics

1998-05-21

1999-12-21

Miska, Vit

Horology: time measuring systems or devices

Time interval

Electrical or electromechanical

324 731, 324658, 324686, 327 46, G04F 800, G01R 1512, G01R 2726

Patent

active

060058293

ABSTRACT:
A reference ring oscillator circuit (RROC) is used to determine timing characteristics of a test interconnect structure in an integrated circuit. The RROC includes an odd number of inverters coupled together in a ring manner and has defined test segments at which a test interconnect can be loaded. Reference timing characteristics of the unloaded RROC are determined according to a calibration method including the steps of: (a) directly measuring signal propagation delay through each segment of the RROC; (b) modeling each test segment using an RC tree type reference circuit model having reference elements; (c) simulating the reference circuit model to provide a functional relationship between two reference capacitors; (d) defining upper and lower bounds for propagation delay through the test segment in terms of the reference elements; (e) determining values for the reference capacitor elements; and (f) measuring a reference frequency of oscillation of the unloaded RROC. After calibration, a test frequency of oscillation of the RROC is measured while a test interconnect structure is loaded onto a test segment. The period of the reference frequency is subtracted from the period of the test frequency. A time difference between the two periods is attributed to increased signal propagation delay through the RROC as a result of loading the test interconnect structure onto the test segment. Based on the measured time difference and determined reference timing characteristics of the test segment, timing characteristics of the test interconnect structure are determined.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 4792932 (1988-12-01), Bowhers et al.
patent: 4795964 (1989-01-01), Shetti
patent: 4878209 (1989-10-01), Bassett et al.
patent: 4890270 (1989-12-01), Griffith
patent: 5083299 (1992-01-01), Schwanke et al.
patent: 5294559 (1994-03-01), Dcthimy
patent: 5606567 (1997-02-01), Agrawal et al.
patent: 5625288 (1997-04-01), Snider et al.
"Signal Delay in RC Tree Networks," IEEE Transactions on Computer-Aided Design, vol. CAD-2, No. 3, Jul. 1983, pp. 202-211.

Affiliated with

Also associated with

Rating

Method for characterizing interconnect timing characteristics does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for characterizing interconnect timing characteristics, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for characterizing interconnect timing characteristics will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-511920