Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-06
2003-05-13
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C002S011000
Reexamination Certificate
active
06564366
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the physical design of electronic devices, and, more particularly, to channel routing.
BACKGROUND OF THE INVENTION
Computer aided design plays a key role in providing electronic circuits with very large scale integration (VLSI) on the market. A useful reference is [1] Naveed Sherwani: “Algorithms for VLSI Physical Design Automation”, Second Edition, Kluwer Academic Publishers, Boston, Dordrecht, London, 1995, ISBN 0-7923-9592-1. According to reference [1], the VLSI design cycle usually comprises system specification, functional design, logic design, circuit design, physical design, fabrication, packaging, testing and debugging. The physical design level has several stages, such as partitioning, floorplanning, placement, routing, and compaction. Iterations are common so that some steps are performed twice or more often. In the placement stage, the exact locations of circuit blocks and their terminals are determined and a list for interconnection nets (i.e. a netlist) between the terminals is generated. Routing is the process of finding geometric layouts for all nets in so-called routing regions between the blocks.
A channel is conveniently referred to in the art as a routing region bounded by two parallel rows of terminals. The distance between the rows, often referred to as “channel height”, should be minimized to save silicon. The estimation of the channel height is very important for floorplanning iterations.
Further references for channel routing are: [2] Akihiro Hashimoto and James Stevens: “Wire routing by optimizing channel assignment within large apertures”, Proceedings of the 8th Design Automation Workshop, 1971, pages 155-169; [3] David N. Deutsch: “A ‘Dogleg’ Channel Router”, Proceedings of the 13th Design Automation Workshop, 1976, pages 425-433; [4] Howard H. Chen and Ernest S. Kuh: “Glitter: A Gridless Variable-Width Channel Router”, IEEE Transactions on Computer-Aided Design, vol. CAD-5. No. 4, October 1986, pages 459-465; [5] James Reed, Alberto Sangiovanni-Vincentelli and Mauro Santomauro: “A New Symbolic Channel Router: YACR2”, IEEE Transactions on Computer-Aided Design, vol. CAD-4, No. 3, July 1985, pages 208-219; and [6] Bryan Preas: “Channel Routing With Non-Terminal Doglegs”, Proceedings of European Design Automation Conference, Glasgow, Scotland, 1990, pages 451-458.
The present invention seeks to provide an improved method to optimize channel routing which mitigates or avoids disadvantages and limitations of the prior art.
REFERENCES:
patent: 5272645 (1993-12-01), Kawakami et al.
patent: 5841664 (1998-11-01), Cai et al.
patent: 6014507 (2000-01-01), Fujii
patent: 6253363 (2001-06-01), Gasanov et al.
patent: WO 97/34245 (1997-09-01), None
patent: WO97/34245 (1997-09-01), None
patent: WO 00/22554 (2000-04-01), None
Naveed Sherwani: “Algorithms for VLSI Physical Design Automation”, Second Edition, Kluwer Academic Publishers, Boston, Dordrecht, London, 1995, ISBN 0-7923-9592-1, pp. 267-344.
Akihiro Hashimoto, James Stevens: “Wire Routing by Optimizing Channel Assignment within Large Apertures”, Proceedings of the 8thDesign Automation Workshop, 1971, pp. 155-169.
David N. Deutsch: “A ‘Dogleg’ Channel Router”, Proceedings of the 13thDesign Automation Workshop, 1976, pp. 425-433.
Howard H. Chen, Ernest S. Kuh: “Glitter: A Gridless Variable-Width Channel Router”, IEEE Transactions on Computer-Aided Design, vol. CAD-5, No. 4, Oct. 1986, pp. 459-465.
James Reed, Alberto Sangiovanni-Vincentelli, Mauro Santomauro: “A New Symbolic Channel Router: YACR2”, IEEE Transactions on Computer-Aided Design, vol. CAD-4, No. 3, Jul. 1985, pp. 208-219.
Bryan Preas: “Channel Routing with Non-Terminal Doglegs”, Proceedings of European Design Automation Conference, Glasgow, Scotland, 1990, pp. 451-458.
Preas, “Channel Routing With Non-Terminal Doglegs,” IEEE, pp. 451-458 (1990).
Chen et al., “Giltter: A Gridless Variable-Width Channel Router,” IEEE, pp. 459-465 (1986).
Reed et al., “A New Symbolic Channel Router: YACR2,” IEEE, pp. 208-219 (1985).
Marchenko Alexander M.
McGuinness Patrick
Plis Andrey P.
Sotnikov Mikhail A.
Garbowski Leigh M.
Motorola Inc.
LandOfFree
Method for channel routing, and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for channel routing, and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for channel routing, and apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3052476