Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-05-25
2001-08-07
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06272668
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer aided engineering electronics design tools and more particularly to a new method used within such tools as applied to the layout of custom integrated circuits using standard cell libraries.
BACKGROUND OF THE INVENTION
Computers have long been utilized to assist engineers in the design of electronic circuits, in particular to assist in the design of integrated circuits. Computer aided engineering (hereinafter CAE) design tools assist the user in the initial design of functional circuitry through the use of a graphical user interface. In general, such CAE design tools permit a user to select an electronic component useful for the intended application from a menu of components known to the system. Next, the tools typically permit a user to place a graphical representation of the selected component on the graphic display screen. Appropriate graphical connections, representing electrical interconnections, between the newly placed component and previously placed components are then “drawn” by the user through the graphical user interface. Tools such as described above which interact with a user to create a graphical representation of the intended application circuit are often referred to as design capture tools.
Following design capture, many other types of CAE tools are known to assist a design engineer in other aspects of the application circuit design. CAE tools are known to perform simulation of the circuits to help locate functional errors in the design. Other tools are used to perform physical layout of the circuit either in the form of discrete components on a printed circuit board, or in the form of custom circuits within an integrated circuit package (known as application specific integrated circuits and hereinafter referred to as ASIC).
ASICs may be designed and implemented using a variety of different chip design products and methods. These methods include “full custom” chip design in which a designer plans the layout and interconnection of every component down to the lowest levels such as individual transistors, capacitors, resistors and the like. Full custom chip design permits the designer to carefully plan every aspect of the chip design to optimize for performance, power management, and physical size. Though full custom chip design allows for the maximum flexibility in design choices, there is usually a significant cost due to complexity of the design and manufacturing processes.
The complexity of full custom chip design is somewhat reduced by use of “gate arrays” in ASIC design. Gate arrays are ASICs in which the designer uses standard components having a higher level of integration to implement the ASIC rather than using exclusively individual transistors and other low level components. In gate array ASIC designs, a designer constructs the desired application circuit utilizing higher level components such as logic gates. A designer may more rapidly design and implement an ASIC using these higher level components but some flexibility may be sacrificed in areas such as performance. “Standard cell” design tools and methods provide component libraries with still higher levels of integration to thereby further simplify the design process. In standard cell design processes, a designer selects among standard functional cells such as adders, decoders, flip-flops, latches, multiplexors, etc. The use of these standard cells which have a higher level of integration further enhances the speed with which a designer may implement an ASIC.
The process of “laying out” an ASIC involves determining a physical placement of the desired circuit components within the integrated circuit (hereinafter IC) package design in such a way as to optimize for parameters such as performance, physical space, and power dissipation. The layout tasks include placement of the desired components as well as routing of interconnection conductor signal paths between the components. In full custom ASIC designs, the designer may interact with CAE tools to control the placement and routing of each low level component in the ASIC. Placing related components closer to one another may improve performance, for example, by reducing the capacitive loads due to length of the interconnection leads between signals to thereby reduce the propagation delays between components. The layout process involves tradeoffs in several interrelated aspects of the ASIC design. Often, a placement of a component in one location within the ASIC will improve the circuit's performance with respect to one parameter but degrade the performance with respect to another parameter. Or a particular placement may improve performance relative to one interconnect path but degrade performance for another path. In gate array or standard cell ASIC designs, other physical constraints of the ASIC layout are imposed by the physical construction of the components within the manufactured IC package. CAE tools typically automate the placement and layout of the components within the gate array or standard cell IC package while attempting to satisfy, primarily, surface area design constraint specifications.
Balancing these tradeoffs can require changing, or swapping, a component selected by the designer to a functionally equivalent component optimized for a different performance, area, or power dissipation goal. Clearly, it is known in the art for a designer to perform such swapping of components manually by iteratively re-designing and analyzing the ASIC. Determining the appropriate balance of these tradeoffs requires analysis of the ASIC design. To analyze an ASIC design with respect to timing, a designer first specifies timing constraints for input or output connections to pins on the IC package for connecting the ASIC chip to other devices. Next, the designer uses CAE analysis tools to determine if the design meets the specified constraints.
Static timing analysis CAE tools are used to automate computation of timing performance of signals within the ASIC design. An ASIC designer, aided by CAE tools, compares the timing estimates produced by such static timing analysis tools to the design constraints to determine whether all constraints have been met. Simulation CAE tools are also common to simulate the actual operation of the ASIC design against a set of test input vectors to determine whether the ASIC design violates any functionality or timing constraints when simulating operation on actual test data inputs. Prior CAE tools, often in conjunction with the designer's manual intervention, iteratively attempted many component placement options to correct any violations of the specified constraints. In the event no satisfactory placement could be determined, CAE design tools informed the user to permit correction of the violation by re-design of the ASIC. A designer could then correct the violation by selecting an alternate component with different operating characteristics.
In standard cell design methodologies, as well as other methods, it is common for a CAE design tool to provide a library of available components which include a variety of functionally equivalent components each having different operating characteristics (such as variable timing specifications or drive power etc.). It is a time consuming process for a designer to manually review the simulation or static timing analysis results and redesign the ASIC to swap components in hopes of eliminating the design constraint violations. In addition, the process could be iterative in that a possible component swap selection may improve design margins with respect to constraints for some interconnect paths while degrading margins in other interconnect paths. The designer must typically verify timing constraints to evaluate the efficacy of the possible component selected for the swap. Several re-design, re-simulate iterations may be required to find an appropriate alternate component selection to resolve any constraint violations.
Methods common to prior CAE design tools attempt to assist the designer in automating the placemen
Hyundai Electronics America Inc.
Kik Phallaka
Smith Matthew
Townsend and Townsend / and Crew LLP
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