Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
2000-02-21
2001-11-13
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S289000, C438S291000, C438S532000
Reexamination Certificate
active
06316341
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for DRAM fabrication, and more particularly, to the cell pass transistor design in DRAM fabrication.
2. Description of the Prior Art
As circuitry density continues to increase, there is a corresponding drive to produce smaller and smaller field effect transistors. Field effect transistors have typically been formed by providing active areas within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. One recent technique finding greater application in achieving reduced transistor size is to form field transistors with thin films, which are commonly referred to as “thin film transistor” (TFT) technology.
FIG. 1A
shows a top view in the fabrication of a conventional MOS structure, and
FIGURE 1B
shows a flowchart in the fabrication of the conventional MOS structure. Conventionally, a resist layer is patterned and first P-type ions are then implanted to form a well implantation region in the silicon substrate
100
. Moreover, second P-type ions are implanted to form a field implantation region in the silicon substrate
100
. Consequentially, third P-type ions are implanted to form a punchthrough implantation region in the silicon substrate
100
. Finally, fourth P-type ions
110
are implanted to form a threshold implantation region in the silicon substrate
100
. The threshold implantation region is formed to implant a dosage between about 1.0 E 13-1.0 E 18 atoms/cm
2
. Finally, the resist layer is removed. When DRAM technology enters 0.18 &mgr;m and below, the substrate convention of the cell pass transistor substrate concentration (Nsub) must increase as high as 1.0 E 18 to control cell transistor short channel effect. But this high cell pass transistor substrate concentration (Nsub) will induce more junction leakage for P/N junction, decreasing the refresh time capability.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for fabricating a cell pass transistor for a DRAM. Therefore, short channel effect of cell transistor can be under adequate control. Furthermore, junction leakage can be reduced for P/N junction of bit-line contact and storage node area. In addition, the refresh time capability of the DRAM can be increased.
In one embodiment, the present invention provides a MOS structure, which can reduce junction leakage for P/N junction and increase the refresh time capability. A method for DRAM fabrication comprises providing a semiconductor substrate having at least an isolation device therein. The isolation device defines an active area adjacent thereto on the semiconductor substrate. A first photoresist layer is formed on the semiconductor substrate, which exposes the active area in a first direction. The first conductive ions are implanted to form a well region in the semiconductor substrate, and the second conductive ions are implanted to form a field implant region in the semiconductor substrate. The third conductive ions are implanted to form a punchthrough implant region in the semiconductor substrate. Then the first photoresist layer is removed, and a second photoresist layer is formed on the semiconductor substrate. The second photoresist layer exposes the active area in a second direction different from the first direction. The fourth conductive ions are implanted to form a threshold implant region, and then the second photoresist layer is removed.
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Luu Chuong
Smith Matthew
United Microelectronics Corp.
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