Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-07-15
2008-07-15
Cho, James H (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S031000
Reexamination Certificate
active
07400165
ABSTRACT:
An improved driver and ODT impedance calibration techniques of a synchronous memory device are provided. The impedance calibration is performed by generating a calibration enable signal showing a calibration operation mode entry. The code signals for an ODT calibration are generated for every predetermined interval of time. A first control signal is generated based on the calibration enable signal. A final code signal of the sequentially generated code signals is latched by the first control signal to use as a driver and ODT impedance calibration signal.
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patent: 6762620 (2004-07-01), Jang et al.
patent: 7292953 (2007-11-01), Jung
patent: 1020050012931 (2005-02-01), None
Cho James H
Hynix / Semiconductor Inc.
Ladas & Parry LLP
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