Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement
Reexamination Certificate
2001-04-30
2002-12-17
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Input noise margin enhancement
C326S121000, C716S030000
Reexamination Certificate
active
06496031
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to electronic circuits. More particularly, this invention relates to integrated electronic circuits designed with CMOS Field Effect Transistors (FETs).
BACKGROUND OF THE INVENTION
Integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and other components on a single semiconductor “chip”. The components on a chip are interconnected to perform a given function or number of functions, such as a microprocessor, a programmable logic device (PLD), a electrically erasable programmable memory (EEPROM), a random access memory (RAM), an operational amplifier, or a voltage regulator. A circuit designer typically designs the integrated circuit by creating a circuit schematic indicating the electrical components and their interconnections. Designs can be simulated by computer to verify functionality and ensure performance goals are satisfied.
In the world of electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer aided design (E-CAD) tools. Electronic devices include electrical analog, digital, mixed hardware, optical, electro-mechanical, and a variety of other electrical devices. The design and the subsequent simulation of any circuit board, VLSI chip, or other electrical device via E-CAD tools allows a product to be thoroughly tested and often eliminates the need for building a prototype. Thus, today's sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools must deal with an electronic representation of the hardware device. A “netlist” is one common representation of a hardware device. A “netlist” is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design tools. A netlist typically comprises information on circuit components and the interconnections between those components.
Two forms of a netlist are the flat netlist and the hierarchical netlist. Often a netlist will contain a number of circuit “modules” which are used repetitively throughout the larger circuit. A flat netlist contains multiple copies of circuit modules essentially containing no boundary differentiation between circuit modules and other components in the device. By way of analogy, one graphical representation of a flat netlist is simply the complete schematic of the circuit device represented with primatives only.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module that may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist would show the basic and/or non-repetitive devices in a schematic form and the more complex and/or repetitive circuit modules would be represented by “black boxes.” A black box is a system or component whose inputs, outputs, and general function are known, but whose contents are not shown. These “black box” representations may mask the complexities of the circuit allowing a level of abstraction that may show only inputs and outputs or some other small set of information.
The design of an integrated circuit can be represented at different levels of abstraction, such as the Register-Transfer level (RTL) and the logic level, using a hardware description language (HDL). VHDL and Verilog are examples of HDL languages. At any abstraction level, an integrated circuit design may be specified using behavioral or structural descriptions or a mix of both. At the logical level, the behavioral description is specified using boolean equations. The structural description is represented as a netlist of primative cells. Examples of primitive cells are full-adders, NAND gates, latches, and D-Flip Flops.
Systems may use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems may perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally such systems may operate by identifying certain critical timing paths, then evaluating the circuit to determine whether timing violations may occur through the critical paths. Timing specifications may be provided to such systems by way of a configuration file.
One such system is marketed under the name PathMill, by EPIC Design Technology, Inc. (purchased by Synopsys). PathMill is a transistor-based analysis tool used to find critical paths and verify timing in semiconductor designs. Using static and mixed-level timing analysis, PathMill processes transistors, gates, and timing models. It also calculates timing delays, performs path searches, and checks timing requirements. PathMill can analyze combinational designs containing gates, and sequential designs containing gates, latches, flip-flops, and clocks. Combinational designs are generally measured through the longest and shortest paths.
While tools such as these are useful for the design verification process after layout, there are various shortcomings in the PathMill product and other similar products. For example, there is a often a need to identify gates such as NAND gates and NOR gates from a transistor level circuit design, in order to verify that certain design criteria have not been violated. For example, it is sometimes desirable to insure that the PFET (P-channel Field Effect Transistor) to NFET (N-channel Field Effect Transistor) transistor width ratio, (W
p
/L
p
)/(W
n
/L
n
), is within a certain predefined range for certain gates (e.g., NOR and NAND gates). The PFET-to-NFET transistor width ratio is also dependent on the input voltages supplied to the gates. Accordingly, there is a need to provide a design tool that evaluates a netlist or other electronic file representative of an electronic circuit to identify the PFET-to-NFET transistor width ratios of static gates based on the inputs to these gates.
SUMMARY OF THE INVENTION
In a preferred embodiment, the invention provides a more accurate PFET(P-type Field Effect Transistor) transistor width to NFET (N-type Field Effect Transistor) transistor width ratio, P/N, of static gates, for use with circuit design tools. The invention identifies a maximum and minimum P/N ratio for each possible logical input combination to a static gate. A maximum and minimum P/N ratio is then selected from the P/N values calculated for each logical input combination. The maximum and minimum P/N values may then be used with circuit design tools to evaluate noise problems with static gates.. This method enables circuit designers to better design VLSI chips and as a result decrease the chances that hardware will have design flaws.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawing, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5038192 (1991-08-01), Bonneau et al.
patent: 2002/0004932 (2002-01-01), Shau
Keller S Brandon
Rogers Gregory D
Le Don Phu
Pessetto John E.
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