Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-04-27
2002-09-03
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S095000, C326S112000
Reexamination Certificate
active
06445213
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the design of dynamic logic devices. More specifically, the present invention relates to calculating dynamic logic block propagation delay targets using time borrowing.
2. Description of the Related Art
Certain styles of CMOS dynamic logic designs have an overlapping clocking structure that allow slower dynamic logic gates to borrow evaluation time from faster dynamic logic gates.
FIG. 5
illustrates an example of an overlapping clock structure that is part of the logic synchronization structure found in N-NARY logic. The logic synchronization illustrated in
FIG. 5
is describe in greater detail in U.S. Pat. No. 6,118,304 to Potter et al., which is incorporated by reference into this disclosure. Further, N-NARY logic is described in greater detail in U.S. Pat. No. 6,069,497 to Blomgren et al., which is incorporated by reference into this disclosure.
FIG. 5
illustrates
4
overlapping clocks, CLK
0
, CLK
1
, CLK
2
, and CLK
3
. The
4
clocks can be derived from a single master global clock (not shown). As is typical to various types of dynamic logic, the clock cycle of an individual clock is divided into a precharge phase, tp, and an evaluate phase, te. The precharge phase tp is the part of the clock cycle where the PFETs of a dynamic logic gate are precharging the evaluate nodes of the logic gate, and the evaluate phase te is the part of the clock cycle where the logic gate evaluates the inputs of the gate to produce an output. A feature of the logic synchronization of N-NARY logic is the evaluate wave window
76
where 2 or more clocks are in the evaluate cycle at any given point in time. The evaluate wave and its overlapping clock structure of this technique of logic synchronization allows N-NARY logic to be designed without latches, buffers, or other types of delay devices in the critical signal path.
The design tool of the present invention is suitable for use in the design of N-NARY logic with the logic synchronization illustrated in FIG.
5
. Further, the present invention is suitable for use in the design of other types of dynamic logic that use overlapping clock structures such as the logic and clocking described in the following patents and articles: U.S. Pat. No. 5,434,520 to Yetter et al.; U.S. Pat. No. 5,517,136 to Harris et al.; Harris, D., and Horowitz, M., Skew-Tolerant Domino Circuits, IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp. 1702-1711 (November 1997); U.S. Pat. No. 5,880,609 to Klass et al.; U.S. Pat. No. 5,983,013 to Rogers et al.; U.S. Pat. No. 6,018,254 to Rogers et al.; all of which are incorporated by reference into this disclosure.
Time borrowing, as illustrated in the above patents and articles, can be used to slow down complex logic gates and or speed up simple logic gates. Without time borrowing, the slowest logic gate in the design would determine the clocking speed for a specified block of logic in the design. With time borrowing, the slowest logic gate can borrow time from preceding or succeeding faster logic gates. Therefore, the clocking speed is no longer constrained by the slowest logic gate, but it is determined by the arrangement of logic gates on the logic paths between the inputs and outputs of the specified block of dynamic logic.
In a block of dynamic logic where the logic gate propagation delays are not all equal, a certain amount of time borrowing will naturally occur, and the clocking speed of the logic block may be increased until the logic block fails to operate. A faster design for the logic block can typically be obtained if time borrowing is planned, i.e. certain logic gates are deliberately designed to be slow and certain logic gates are deliberately designed to be fast. One way to optimize the clocking speed of dynamic logic is for a logic designer to carefully plan the logic gate propagation delays so that the logic block speed is optimized. Hand optimization of dynamic logic is a time consuming task however for a logic designer. Thus, a more systematic and automated method is required to analyze a dynamic logic circuit block and determine the propagation delay targets for the dynamic logic gates that comprise the block of logic.
SUMMARY OF THE INVENTION
The present invention is a dynamic logic propagation delay targeting tool that calculates the propagation delay of a signal in a specified block of dynamic logic. The present invention comprises a gate target delay initializer, a levelizer, a backward logic scanner, a forward logic scanner, a gate target delay incrementor, and a gate target delay comparator that together calculates the propagation delay of a signal.
The gate target delay initializer of the present invention calculates the initial delay targets for all logic gates in the specified block of dynamic logic.
The levelizer of the present invention levelizes all the logic gates in the specified block of logic where the levelizing of all the logic gates further comprises ordering the logic gates in the logic block to analyze the propagation of the signal through the logic block.
The present invention further comprises a backward logic scanner that backward scans the logic gates of the specified block of logic and then calculates for each individual scanned logic gate an output backward surplus of delay at the individual scanned logic gate's output and an input backward surplus of delay at the individual logic gate's input. The output backward surplus of delay at the individual scanned logic gate's output is defined to be the minimum of all the backward surpluses of delay at the inputs of all the logic gates that are connected to the output of the individual scanned logic gate. And, the input backward surplus of delay at the individual logic gate's input is equal to the nominal phase delay−(Current Delay Target of Gate+Wire Delay at output of Gate)+Backward surplus at output of Gate.
The present invention further comprises a forward logic scanner that forward scans the logic gates of the specified block of logic and then calculates for each individual scanned logic gate an input forward surplus of delay at the individual scanned logic gate's input and an output forward surplus of delay at the individual scanned logic gate's output. The input forward surplus of delay at the individual scanned logic gate's input is defined to be the minimum of all the forward surpluses of delay at the outputs of all the logic gates that are connected to the input of the individual scanned logic gate. And, the output forward surplus of delay at the individual scanned logic gate's output is equal to the nominal phase delay−(Current Delay Target of Gate+Wire Delay at output of Gate)+Forward surplus at input of Gate.
The present invention further comprises a gate target delay incrementor that increments delay targets if a positive surplus of delay exists for each individual scanned logic gate of the specified block of logic where the positive surplus of delay is defined as the (Forward surplus at output of Gate+Backward surplus at output of Gate)>=0.
The present invention further comprises a gate target delay comparator that compares the current delay targets of each individual scanned logic gate of the specified block of logic to the prior delay targets of each individual scanned logic gate of the specified block of logic to further increase the delay targets of all the scanned logic gates of the specified block of logic.
REFERENCES:
patent: 5434520 (1995-07-01), Yetter et al.
patent: 5517136 (1996-05-01), Harris et al.
patent: 5745724 (1998-04-01), Favor et al.
patent: 5880609 (1999-03-01), Klass et al.
patent: 5983013 (1999-11-01), Rogers et al.
patent: 6018254 (2000-01-01), Rogers et al.
patent: 6118304 (2000-09-01), Potter et al.
patent: 6201415 (2001-03-01), Manglore
patent: 6324664 (2001-11-01), Farwell et al.
Harris, Skew-Tolerant Domino Circuits, IEEE Journal of Solid-State Circuits, Nov. 1997, 1702-1711, vol. 32, No. 11.
Blomgren James S.
Glowka Donald W.
Horne Stephen C.
Vijayan Gopal
Booth Matthew J.
Booth & Wright LLP
Intrinsity, Inc.
Le Don Phu
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