Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2006-09-12
2006-09-12
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S022000, C710S113000, C710S241000, C710S308000
Reexamination Certificate
active
07107374
ABSTRACT:
A processor is connected to a configurable system interconnect (CSI) bus. A CSL is connected to the CSI bus. The CSL comprises a first set of signal lines to send a data transfer request and a second set of signal lines to receive a grant associated with the data transfer request. A bus master unit (BMU) is coupled with the CSL through the first set of signal lines and the second set of signal lines. The BMU is connected to the CSI bus. The BMU arbitrates to take control of the CSI bus on behalf of the CSL enabling the CSL to perform data transfer to or from the CSI bus bypassing the processor.
REFERENCES:
patent: 5175836 (1992-12-01), Morgan
patent: RE34363 (1993-08-01), Freeman
patent: 5361373 (1994-11-01), Gilson
patent: 5499385 (1996-03-01), Farmwald et al.
patent: 5668815 (1997-09-01), Gittinger et al.
patent: 5677638 (1997-10-01), Young et al.
patent: 5687325 (1997-11-01), Chang
patent: 5710891 (1998-01-01), Normoyle et al.
patent: 5774684 (1998-06-01), Haines et al.
patent: 5834947 (1998-11-01), Cedar et al.
patent: 5862353 (1999-01-01), Revilla et al.
patent: 5890002 (1999-03-01), Li et al.
patent: 5901295 (1999-05-01), Yazdy
patent: 5935230 (1999-08-01), Pinai et al.
patent: 5936424 (1999-08-01), Young et al.
patent: 6047336 (2000-04-01), Green, III et al.
patent: 6085317 (2000-07-01), Smith
patent: 6154793 (2000-11-01), MacKenna et al.
patent: 6212625 (2001-04-01), Russell
patent: 6223238 (2001-04-01), Meyer et al.
patent: 6347346 (2002-02-01), Taylor
patent: 6363445 (2002-03-01), Jeddeloh
patent: 6467009 (2002-10-01), Winegarden et al.
patent: 6601126 (2003-07-01), Zaidi et al.
patent: 6658502 (2003-12-01), Story et al.
patent: 6691266 (2004-02-01), Winegarden et al.
patent: 6792527 (2004-09-01), Allegrucci
patent: 2003/0182486 (2003-09-01), Taylor et al.
patent: 0062431 (1942-10-01), None
patent: 0361525 (1990-04-01), None
J.C. Logue and W.W. Wu, “System Master Slice for Fast Turnaround Time,” XP000714153, IBM Technical Disclosure Bulletin, vol. 26, No. 3B, pp. 1531-1532 (Aug. 1, 1983).
Steve Farrer, “High Speed Numerics with the 80186/80188 and 8087,” Intel Corporation, Embedded Applications vol. 1, Application Note AP-258, pp. ix-xii and 4-1 to 4-18 (1995).
Intel Corporation, “Embedded Microprocessors:Intel 386™ Processors, Intel376 Processors and Peripherals, 80186/80188 Family,” pp. ix-x and 1-1 to 1-32 (1995).
Intel Corporation, “Peripheral Components:Chips Sets, PC I/O Peripherals, Memory Controllers, Keyboard Controllers, Support Peripherals,” pp. ix-xi and 1-57 to 1-247 (1995).
King John J.
Patel Nimesh
Perveen Rehana
Sokoloff Blakeley
XILINX Inc.
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