Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2000-12-15
2003-09-23
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S128000, C438S129000, C438S014000, C438S017000, C438S005000, C438S010000, C438S011000, C438S012000
Reexamination Certificate
active
06623997
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to optical devices and more particularly to a method for performing burn-in processing of optical transmitters.
BACKGROUND ART
Increasingly, data communications involve transmissions by optical sources that can deliver tremendous volumes of digitized information as pulses of light. This is especially true for many communication companies that utilize laser diodes and optical fibers as their primary means for the transmission of voice, television and data signals for ground-based communications networks.
To achieve high bandwidth, laser diodes such as edge-emitting lasers and Vertical Cavity Surface Emitting Lasers (VCSELs) are commonly utilized as optical sources. These types of laser diodes are preferred due to their minute dimensions. For example, the typical VCSEL is measured in the order of micrometers. Consequently, an array of laser diodes can be integrated into a system to achieve high bandwidth transmissions.
In the manufacturing and production of VCSEL arrays, such as 1×12 or 1×4 parallel channel optical arrays, it is critical that arrays that are subsequently utilized manifest target optical and electrical characteristics. To determine whether the VCSEL arrays will be operating at their target levels, it is necessary to subject each diode of the array to a burn-in process. That is, each VCSEL must be submitted to a rigorous quality control (QC) procedure that includes subjecting the VCSEL to a constant current at an elevated temperature for an extended time period. The burn-in current can be selected to be at a level that is higher than the standard operating current, since the QC procedure is a short-term test of whether the VCSELs will provide long-term performance during actual operating conditions. Similarly, the burn-in temperature is selected to be at a higher temperature than the anticipated operating temperature. Finally, the burn-in time period is selected on the basis of the type, specification and stringency of the devices.
Currently, the burn-in process for VCSELs is largely performed at the packaging level. That is, quality control is performed on an individual VCSEL array after the VCSEL array has been die attached and wire bonded in package form. In fact, burn-in is sometimes executed until the array has been connected to a nearly finished product having electrical circuitry, such as a feedback circuit. If any VCSEL within the array is determined to be defective or is not in compliance with the specifications as required following a burn-in process, the entire assembly is discarded. This is wasteful and expensive in terms of material, use of fabrication resources, and labor costs.
Consequently, what is needed is an efficient burn-in process that allows the burn-in testing of optical arrays in such a manner as to verify that each optical transmitter is capable of operating at its target performance level prior to the packaging level.
SUMMARY OF THE INVENTION
A submount substrate is used while in an intact condition for its original purpose of enabling simultaneous burn-in processing for a number of arrays of optical transmitters, and is used in a segmented condition for its secondary purpose of providing a means for connecting individualized arrays to other electrical components of devices in which the arrays are to operate. That is, the submount substrate is specifically designed to provide connectivity between the arrays and burn-in equipment during the testing stage, but is also designed to be segmented and used in the final packaging stage.
The arrays of optical transmitters may be fabricated using known techniques. In the preferred embodiment, the optical transmitters are laser diodes and are most preferably Vertical Cavity Surface Emitting Lasers (VCSELs). VCSELs are formed using integrated circuit fabrication techniques. VCSELs include a number of patterned layers that cooperate to emit light when connected to a drive current. As one example, each VCSEL array may be a side-by-side arrangement of twelve VCSELs to be used in a 1×12 parallel channel optical transmitter or transceiver module. In accordance with the invention, the arrays of laser diodes are conventionally fabricated on a semiconductor substrate that is then diced to form the individual arrays. While not critical to the invention, some testing of the laser diodes may be performed prior to the dicing step.
After the arrays of laser diodes have been fabricated and separated into discrete chips, the arrays are mechanically and electrically coupled to the submount substrate. In the preferred embodiment, the submount substrate is a semiconductor substrate and is most preferably a silicon wafer. Thus, conventional integrated circuit fabrication techniques may be used to form contact patterns along one surface of the submount substrate. The contact patterns provide a repeating arrangement of array-receiving areas. The transmitter arrays are connected to the submount substrate at the array-receiving areas. Wire bonding and/or flip chip techniques may be employed in connecting the transmitter arrays to the submount substrate.
In addition to the contact patterns, the submount substrate includes electrical paths. The electrical paths provide connections between the burn-in equipment and the individual laser diodes of the arrays. In the preferred embodiment, the submount substrate is a silicon wafer having a matrix of the contact patterns in a central region and having probe contact pads on a peripheral region. The probe contact pads are used to connect the silicon wafer to other circuitry, such as burn-in control circuitry on a printed circuit board. Also in the preferred embodiment, the silicon substrate includes integrated resistors, with each laser diode having at least one dedicated resistor for properly biasing the laser diode. Preferably, the voltage drop across the dedicated resistor is monitored and is used as a feedback mechanism for maintaining the laser diodes at the burn-in current that is selected for the burn-in process.
The burn-in process may involve a rigorous procedure in which the laser diodes are operated at the burn-in current for an extended period of time and at an elevated temperature. For example, the temperature may be maintained within the range of 80° C.-120° C. and the burn-in time may be in the range of 24 hours to 72 hours. The burn-in current is selected to have an amperage that is slightly below the overdrive current, which is the maximum current at which the laser diode can reliably function without sustaining performance degradation or failure. As one example, a VCSEL may have a burn-in current of approximately 30 milliamperes.
Following the completion of the burn-in period, each laser diode of each array is tested. In the preferred embodiment, the testing occurs while the submount substrate is still intact. Each laser diode is probed to determine its operational state. Those arrays that have at least one laser diode that is detected as being non-operational are identified as defective. The submount substrate is then diced into segments in which each segment is an assembly of an array chip mounted on a submount chip. The assemblies having identified defective arrays are discarded, while the remaining assemblies are used for manufacturing optical devices, such as transmitter modules and transceiver modules. In the preferred embodiment, the connection of the assembly to another component of an optical device is achieved by wire bonding from the array chip. Thus, the submount chip provides the mechanical connection, while electrical connections are made directly to the array chip.
REFERENCES:
patent: 5493577 (1996-02-01), Choquette et al.
patent: 5617036 (1997-04-01), Roff
Chang James
Kaneshiro Ronald T.
Therisod Stefano G.
Duong Khanh
Zarabian Amir
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