Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-02-27
1998-10-06
Lall, Parshotam S.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
395391, 39580023, 711145, G06F 1200
Patent
active
058193081
ABSTRACT:
An improved method and apparatus for buffering and issuing instructions for use with superscalar microprocessors are disclosed. The method comprises the steps of: (a) obtaining an instruction buffer comprising a plurality of entries, each entry comprising a random access memory (RAM) portion and a content addressable memory (CAM) portion for storing result data and source operand tag, respectively, wherein the CAM portion also contains means for linking with an associated RAM portion and the result data contains an instruction; (b) providing a result bus capable of transmitting the result data and a result tag; (c) matching the result tag in the result bus with the source operand tag in the CAM, and writing the result data into the RAM portion of an entry if the result tag in the result bus matches the source operand tag of an associated CAM portion; and (d) issuing ready instructions and changing the source operand tag in a corresponding CAM in such a manner that the entry containing the CAM will be identified as an empty entry so as to all new instruction to be written thereto. Because instructions are stored in the RAM in an out-of-order, a linear systolic array is provided so as to keep the sequence of instructions in order. The linear systolic array, which can be easily compressed, allows the prioritization of instructions for issue among ready instructions, and the handling branch mis-prediction and faults to be implemented.
REFERENCES:
patent: 5285527 (1994-02-01), Crick et al.
patent: 5499204 (1996-03-01), Barrera et al.
patent: 5515518 (1996-05-01), Stiles et al.
patent: 5532693 (1996-07-01), Winters et al.
patent: 5555392 (1996-09-01), Chaput et al.
Zwie Amitai et al.; "Trends in Specialty Memories -from FIFOs to CAMs"; Northcon/93 Conference Record; pp. 200-202, 1993.
Raymond Heald et al.; "A 6-ns Cycle 256-kb Cache Memory and Memory Management Unit"; IEEE Journal of Solid-State Circuits, vol. 28, No. 11; pp. 1078-1083, Nov. 1993.
Chang Ching-Tang
Tien Chien-Kuo
Wang Dze-Chaung
Wu Kun-Cheng
Coulter Kenneth R.
Industrial Technology Research Institute
Lall Parshotam S.
Liauh W. Wayne
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