Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-12-05
2003-09-02
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S701000
Reexamination Certificate
active
06613649
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and particularly to a method of forming isolation for integrated circuits, and more specifically, to a method of forming a shallow.trench isolation.
2) Description of the Prior Art
Semiconductor integrated circuits (ICs) have evolved towards increased density and device shrinkage. One important structure in the manufacture of ICs is isolation structures. Devices formed in the silicon substrate must be isolated from one another. Establishing effective isolation in submicron. ICs in the face of decreased isolation space is a complicated and challenging task.
One conventional-method for isolation involves oxidizing.a bare silicon wafer in a furnace to grow a pad oxide layer The pad oxide layer is most typically formed from silicon dioxide. A nitride layer is then deposited on the pad oxide layer. A masking and etching step is then performed to form trenches. Next, oxide is then deposited in the trenches by chemical vapor deposition (CVD). The CVD oxide is then planarized by a chemical mechanical polishing (CMP).
Planarization by the CMP presents several problems. The removal rate of the CVD oxide by the CMP is higher than the removal rate of the nitride, causing dishing in wide trenches. This dishing.effect degrades the planarity of a layer, and it also impacts the yield of the device. Furthermore, end point detection is not accurate during the CMP because the ratio of the removal rate of the CVD oxide to the removal rate of the nitride is about 3 or 4 to 1. Increasing this ratio to improve end point detection would result in increased dishing under this conventional method. Therefore, a need arises for a simple and efficient method of forming a trench isolation that reduces dishing.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 6,001,706 (Tan et al.) shows a STI planarization process. U.S. Pat. No. 5,928,961 (Lou et al.) shows a STI process using a transition layer. U.S. Pat. No. 5,981,357 (Hause et al.) teaches another STI planarization process. U.S. Pat. No. 5,298,451 (Rao) shows a related STI patent. U.S. Pat. No. 6,117,748 (Lou et al.), U.S. Pat. No. 6,214,69B1 (Wu). and U.S. Pat. No. 61248,667B1 (Kim et al.) show other planarization and STI processes.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a shallow trench isolation (STI) having reduced dishing.
It is an object of the present invention to provide a method for fabricating,a shallow trench isolation (STI) using a buffer layer and chemical mechanical polish (CMP) process having reduced dishing.
It is an object of the present invention to provide a method for fabricating a shallow trench isolation (STI:) using hard mask layer over a buffer layer; the hard mask layer acts as an oxidation barrier during a trench liner oxidation.
An embodiment of the present invention provides a method of manufacturing a shallow trench isolation which is characterized as follows. A pad layer, a polish stop layer, a buffer layer and a hard mask layer are formed over a substrate. The hard mask layer has a hard mask opening. We form a trench opening in the buffer layer, the polish stop layer, the pad layer and form a trenching the substrate using the hard mask layer as an etch mask. We form an oxide trench liner layer along the sidewalls of the trench and an oxide buffer liner layer on the sidewalls of the buffer layer. The invention's hard mask layer prevents the oxidation of the top surface of the buffer layer during the oxidation of the oxide trench liner. This prevents the buffer layer from being consumed by the oxidation and leaves a sufficient thickness of buffer layer to act in the subsequent chemical-mechanical polish (CMP) step. Next, an insulating layer is formed over the hard mask layer and at least partially fills the trench. The insulating layer is chemical-mechanical polished using the polish stop layer as a stop layer. The buffer layer acts to prevent field oxide dishing during the chemical-mechanical polish (CMP). The polish stop layer is removed.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.
REFERENCES:
patent: 5130268 (1992-07-01), Liou et al.
patent: 5298451 (1994-03-01), Rao
patent: 5539229 (1996-07-01), Noble et al.
patent: 5776808 (1998-07-01), Muller et al.
patent: 5786262 (1998-07-01), Jang et al.
patent: 5817568 (1998-10-01), Chao
patent: 5928961 (1999-07-01), Lou et al.
patent: 5981357 (1999-11-01), Hause et al.
patent: 6001706 (1999-12-01), Tan et al.
patent: 6117748 (2000-09-01), Lou et al.
patent: 6121133 (2000-09-01), Iyer et al.
patent: 6214696 (2001-04-01), Wu
patent: 6248667 (2001-06-01), Kim et al.
patent: 6297127 (2001-10-01), Chen et al.
patent: 0031114 (2001-09-01), None
Chen Feng
Goh Wang Ling
Lim Seng-Keong Victor
See Alex
Blum David S
Chartered Semiconductor Manufacturing LTD
Jr. Carl Whitehead
LandOfFree
Method for buffer STI scheme with a hard mask layer as an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for buffer STI scheme with a hard mask layer as an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for buffer STI scheme with a hard mask layer as an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3034742