Semiconductor device manufacturing: process – Chemical etching – Having liquid and vapor etching steps
Reexamination Certificate
2002-04-15
2003-12-16
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Having liquid and vapor etching steps
C438S680000
Reexamination Certificate
active
06664192
ABSTRACT:
FIELD OF THE INVENTION
The method relates generally to integrated circuit processing and fabrication and, more particularly, to metal interconnect structures and the deposition of barrier layers in a selective way.
BACKGROUND OF THE INVENTION
The ongoing focus on miniaturization and the increasing complexity and speed requirements of integrated circuits demand continuously higher density integration. To achieve this, there is an ongoing downscaling in the dimensions of the active devices, as well as of the structures interconnecting these devices. These interconnect structures can comprise multiple metal levels which are, depending on the desired interconnect pattern, either separated from one another by means of interlevel insulating layers or connected to one another by means of a conductive connection through the insulating layer. Besides this downscaling of the dimensions, additional measures are required to be able to meet the stringent speed specifications. Conventionally, the metal levels are aluminum (Al) layers while the insulating layers are oxide layers. In order to reduce the signal delay, one can choose a metal layer with a higher conductivity compared to aluminum and/or choose insulating layers with a lower dielectric constant compared to oxide layers. To meet these objectives copper-containing metal layers and/or copper-containing connections will be introduced in the near future.
The use of copper (Cu) in interconnect structures has some commonly known disadvantages. Cu can have a high diffusion in the surrounding insulating layers, which negatively affects the reliability and the signal delay. Several solutions have been proposed to solve this problem. Materials such as refractory metals have been used as a barrier layer to prevent copper from migrating into the surrounding layers.
The currently used technique inhibits the migration of copper ions in the surrounding layers by depositing a barrier layer in a non-selective way.
FIG. 1
illustrates the resulting structure. The conductive bottom surfaces
10
as well as the insulating sidewalls
12
(which include the trench floors
13
) of the opening in an insulating layer
14
are covered with a barrier material
16
. In case of chemical vapor deposition (CVD), the barrier
16
is conformally deposited. In case of physical vapor deposition (PVD), the coverage of the vertical walls and the bottom of the opening is thinner compared to the coverage of the top of the structure. However, the ratio between vertical and horizontal coverage can be tuned to a certain extent by modifying the process parameters like deposition power, the bias of deposition, etc.
Several problems are related to the deposition of barrier layers. Since the barrier layer is deposited on both the insulating sidewalls
12
and the conductive bottom wall
10
of an opening in an insulating layer
14
,
15
, the occurrence of a barrier layer on the bottom wall
12
causes several inconveniences. When the opening is filled with a metal
18
, the barrier layer
16
between the overlying metal
18
and the underlying metal
20
has a detrimental effect on the electromigration behavior of the structure, since the barrier
16
serves as a flux divergence point for the electrons. Consequently, a discontinuity for the metal atoms occurs with electromigration during subsequent circuit operation.
The presence of the barrier layer
16
on the bottom surface
10
of an opening in an insulating layer creates additional inconveniences. Since the adhesion between the barrier layer
16
and the underlying conductive layer
20
is not always good, the current flowing between the different conductive levels will be influenced, having a negative impact on the reliability and the resistivity of the conductive path.
In U.S. Pat. No. 5,904,565, a direct copper-to-copper connection between different levels in an integrated circuit is disclosed. In a first step, a barrier layer is conformally deposited into the via. In a second step, the barrier layer covering the lower copper level is selectively removed by anisotropically etching. The barrier covering the vertical sidewalls remains. This method implies a more complex process with more process steps than conventional barrier formation, which causes additional difficulties by implementation. Furthermore, the cost will increase.
Consequently, a need exists for a method of forming a direct metal-to-metal contact by selectively depositing a barrier layer on the insulating surfaces of an opening formed in an insulating layer, such that superior conductive behavior of the metal levels in an integrated circuit (IC) can be obtained.
SUMMARY OF THE INVENTION
Methods are described herein for selectively depositing a material, particularly a barrier material, on a substrate. The method selectively provides the material on a first surface while leaving a second surface exposed, where the first and second surfaces differ in material composition. Preferably, the method involves conditioning the first surface to form ligands thereon, and thereafter depositing the barrier layer on the conditioned first surface while avoiding depositing on the second surface.
Desirably, the first surface is of an insulating layer and the second surface is of a conductive layer. More particularly, in the preferred embodiments, a method is described for depositing a barrier layer on part of the sidewalls of an opening passing through at least an insulating layer to a layer consisting essentially of a conductive material is described. This method comprises creating the opening in the insulating layer, conditioning at least insulating sidewalls of the opening to form ligands on these insulating sidewalls, and thereafter depositing the barrier layer on the insulating sidewalls while avoiding deposition of the barrier layer on conductive sidewalls.
In accordance with one aspect of the invention, the method comprises removal of ligands formed on the second surface after conditioning.
In accordance with another aspect of the invention, conditioning results in modification (e.g., chemical or physical modifications) of the first and second surfaces, followed by further modification of the conditioned second surface. The further modification can comprise removal of the conditioning modifications, or converting the conditioning modifications into growth-blocked surface formations. Exemplary further modification includes: heating in a reducing ambient; plasma treatment in a reducing ambient; heating under vacuum or high pressure; or chemical treatment, such as cleaning or a chemical reduction. Alternatively, modification of the second surface can comprise formation of growth-blocking or sacrificial layers, prior to or after the conditioning of first surface.
In an embodiment of this invention, said conditioning is a chemical reaction between chemical molecules being part of said sidewalls of said opening consisting of insulating material and an appropriate atmosphere such that ligands on said sidewalls of said opening are formed. Conditioning can also comprise a chemical reaction between said sidewalls of said opening consisting of said conductive material and an appropriate atmosphere such that ligands on said sidewalls of said opening are formed. Said conditioning can comprise also an additional step being characterized in that said ligands formed on said sidewalls consisting essentially of conductive material are removed.
In accordance with one aspect of the invention, depositing the barrier layer is performed by atomic layer deposition.
In accordance with one aspect of the invention, the opening created in the insulating layer is a via hole, a contact hole or a trench.
In accordance with one aspect of the invention, the insulating material can be silicon dioxide, silicon nitride, silicon oxynitride, a low-k material or a porous material with a low dielectric constant.
In accordance with one aspect of the invention, the ligands are selected from hydroxyl, cyano, NH
2
, NH, fluoro, bromo, iodo, chloro, methyl, alkoxo, &bgr;-diketonato, isopropoxo and other car
Elers Kai-Erik
Haukka Suvi P.
Maex Karen
Saanila Ville Antero
Satta Alessandra
Interuniversitair Microelektronica Centrum (IMEC)
Knobbe Martens Olson & Bear LLP
Nhu David
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