Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
1999-05-24
2003-03-25
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S612000, C438S613000, C257S737000, C257S778000
Reexamination Certificate
active
06537854
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for bonding an IC chip which has corrugated multi-layered bumps to a substrate and devices formed by the method and more particularly, relates to a method for bonding flip chips that are equipped with corrugated multi-layered bumps to a circuit board without using anisotropic conductive films and devices formed by the method.
BACKGROUND OF THE INVENTION
In recent years, liquid crystal display (LCD) panels have been used widely in place of cathode ray tubes (CRT) in electronic display applications. The LCD panel is first assembled together by filling a liquid crystal material inbetween a LCD substrate and a transparent glass cover plate. The LCD substrate consists of a multiplicity of switching, or electronic turn-on and turn-off devices for operating the multiplicity of pixels formed on the LCD panel.
After the assembly of a LCD panel is completed, the panel must be connected to an outside circuit for receiving electronic signals such that images may be produced in the panel. The electronic connections to the LCD panel can be provided by different techniques. A conventional technique for providing electronic signals to a LCD panel is by using a flexible printed circuit board (FPCB) which contains various electronic components welded thereto for providing signals to the LCD. The flexible printed circuit board is frequently manufactured of a conductive copper layer sandwiched between two flexible polyimide cover layers. The flexibility of FPCB is advantageous in the installation of a LCD panel. For instance, a conventional LCD panel may be connected by a FPCB to a printed circuit board (PCB) which has a surface mount technology (SMT) type IC chip mounted on top.
In another conventional technique for bonding a LCD to a PCB, a tape automated bonding (TAB) technique is used. In the TAB bonding technique, a TAB section is used to connect an LCD to a PCB. The TAB section consists of a TAB tape which has an IC chip connected to it through numerous bonding sites. The TAB bonding technique provides the benefit of a compact package so that circuit density can be improved resulting in a lead pitch as low as 60 &mgr;m. The TAB, also known as TCP (tape carrier package) utilizes finely patterned thin metal, i.e., copper foil plated with Au or Sn, in place of wires and connects the metal tips metallurgically to corresponding gold plated bumps that are formed on the aluminum pads on the chip. TAB is preferred in smaller-pitch interconnects for high I/O ULSI devices because it enables smaller pitch and longer span bondings than those available by wire bonding. However, the TAB bonding technique is normally conducted at a higher fabrication cost.
In still another technique for bonding a LCD to a PCB, as shown in
FIGS. 1A and 1B
, a chip on glass (COG) technique is used. In the COG technique, an IC chip
12
can be mounted directly to a glass substrate
14
of an LCD by utilizing solder bumps
16
and an anisotropic conductive film (ACF)
18
. The ACF tape
18
contains electrically conductive particles
20
which are embedded in an insulative material
22
. Positioned under the ACF
18
is the LCD substrate
14
which has conductive elements
24
formed on top. After the IC chip
12
, the ACF
18
and the LCD substrate
14
are pressed together under heat, as shown in
FIG. 1B
, the conductive particles
20
provides electrical communication between the solder bumps
16
and the conductive elements
24
and therefore allowing the IC chip
12
to electrically communicate with the LCD substrate
14
, i.e., the IC chip
12
may be a driver chip which is connected to the drive lines on the LCD. It should be noted that, electrical communication between the solder bumps
16
and the conductive elements
24
is only established where the conductive particles
20
are compressed, i.e., only established anisotropically and selectively. The conductive elements
24
on the LCD substrate
10
is normally formed of indium-tin-oxide (ITO) thin films.
The COG technique may further connect the LCD substrate
14
to a printed circuit board (not shown) or a flexible printed circuit board (not shown). The COG technique therefore relies on bonding with solder bumps
16
formed on an IC chip and the ACF
18
for electrical communications.
The traditional COG technique shown in
FIGS. 1A and 1B
may be carried out in an alternate method of using a liquid adhesive. This is shown in
FIGS. 2A and 2B
. In this alternate COG technique, an IC chip
12
is mounted directly to a glass substrate
14
of an LCD by solder bumps
16
and a liquid adhesive
26
. The liquid adhesive
26
can be suitably an acrylic or an epoxy which can be cured by either an UV light or by heat. The liquid adhesive
26
can be dispensed in droplets such as shown in
FIG. 2A
on top of the glass substrate
14
over the conductive elements
24
formed on the substrate. The conductive elements
24
may be suitably formed of a conductive film such as ITO. After the liquid adhesive
26
is dispensed on the top surface
28
of the glass substrate
14
, the IC chip
12
may be pressed onto the substrate
14
under a suitable pressure and heated to a suitable temperature. The pressure exerted enables the conductive elements
24
to intimately contact the solder bumps
16
such that an ohmic bond is formed thereinbetween. The liquid adhesive
26
fills the gap between the conductive elements
24
or the solder bumps
16
and solidifies after the curing process. The solidified liquid adhesive
26
functions as a stress buffer and a moisture barrier for protecting the bond formed between the conductive elements
24
and the solder bumps
16
from stress fracture or moisture attack. The bonded structure is shown in FIG.
2
B.
As seen in the three conventional techniques for forming a TFT-LCD assembly, each of the techniques has its benefits and disadvantages. For instance, in the first technique of using SMT/FPCB, the circuit density can be increased to achieve a compact package at the expense of using difficult TAB technology and high material costs. In the TAB and COG method, a rework of the assembly such as the removal of a defective IC from a LCD substrate is extremely difficult, if not impossible. For instance, the only possible means for removing an IC chip that is bonded to a LCD substrate is by using a shear force for pushing an IC chip and breaking its bond with the LCD substrate. This is a difficult process and frequently results in the destruction of the entire assembly.
In the present fabrication process for TFT-LCD assemblies, the SMT/FPCB method is frequently used in fabricating lower priced assemblies such as those utilizing small LCD panels. In large LCD panel applications, i.e., such as those used in notebook computers, the TAB bonding method is normally used. The COG method, due to its difficulty in reworking and repair, is also limited to small LCD panel display applications. The TAB process and the COG process are therefore the two major assembling methods used for TFT-LCD assemblies. To sum up, the TAB method can be easily reworked and repaired by removing an IC chip from the TAB tape and furthermore, it is compact in size which allows the achievement of high density packages of up to 60 &mgr;m pitch. However, the TAB process requires complicated fabrication steps which include IC bonding, tape fabrication, inner lead bonding, encapsulation, outer lead bonding and the ACF process.
In the COG process shown in
FIGS. 1A and 1B
, the ACF film
18
used presents numerous problems. First, the cost of the ACF films is high compared to other underfill or stress buffer materials. The high cost is contributed by the gold coating required on the conductive particles or fillers and the epoxy material used in the medium. Secondly, in modem high density circuit designs where the pitch between bumps may be smaller than 50 &mgr;m, the problem of voltage leaks or shorts frequently occurs. Thirdly, due to the presence of electrically conductive particles in the filler material th
Chang Shyh-Ming
Jou Jwo-Huei
Wu Chi-Yuan
Industrial Technology Research Institute
Picardat Kevin M.
Tung & Associates
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