Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-07-31
2003-11-04
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S638000, C438S706000, C438S710000, C134S001100
Reexamination Certificate
active
06642153
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to multi-layered semiconductor structures and more particularly to a method for preventing or avoiding the presence of unetched polymer residues including photoresist remaining in anisotropically etched semiconductor features including trench line features formed in a dual damascene process.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low resistance and capacitance interconnect properties, particularly where submicron inter-layer interconnects and intra-layer interconnects have increasingly high aspect ratios (e.g., an interconnect opening depth to diameter ratio of greater than about 4). In particular, high aspect ratio vias require uniform etching profiles including preventing necking or narrowing of the via opening which detrimentally affects design constraints for electrical resistance in semiconductor device functioning. Such necking or narrowing of the opening can detrimentally affect subsequent processes including adhesion/barrier layer deposition and metal filling deposition frequently resulting in degraded device function including electrical pathway open circuits.
In the fabrication of semiconductor devices, increased device density requires multiple layers, making necessary the provision of a multi-layered interconnect structure. Such a multi-layered interconnect structure typically includes intralayer conductive interconnects and inter-layer conductive interconnects formed by anisotropically etched openings in an insulating layer, often referred to an inter-metal dielectric (IMD) layer, which are subsequently filled with metal. Commonly used inter-layer high aspect ratio openings are commonly referred to as vias, for example, when the opening extends through an insulating layer between two conductive layers. The intra-layer interconnects extending horizontally in the IMD layer to interconnect different areas within an IMD layer are often referred to as trench lines. In one manufacturing approach, trench lines are formed overlying and encompassing one or more vias to form interconnects referred to as dual damascene structures.
In a typical process for forming multiple layer interconnect structure, for example, a dual damascene process, an insulating inter-metal dielectric (IMD) layer is deposited over a conductive area, for example a metallization layer frequently referred to as metal
1
, metal
2
, etc. depending on the number of preceding metallization layers. In one approach to forming a dual damascene structure, vias are first anisotropically etched through the IMD layer by conventional photolithographic and etching techniques. A second anisotropically etched opening referred to as a trench line is then formed according to a second photolithographic patterning process overlying and encompassing the via opening. The via opening and the trench line together makeup the dual damascene structure which is subsequently filled with metal, for example, copper, followed by a CMP planarization process to planarize the wafer process surface and prepare the process surface for formation of another layer or level in a multi-layered semiconductor device.
Signal transport speed is of great concern in the semiconductor processing art for obvious performance reasons. The signal transport speed of semiconductor circuitry, critically affected by the RC time constant of the multi-layer device, varies inversely with the product of resistance and capacitance (RC) of the interconnections. As integrated circuits become more complex and feature sizes decrease, the influence of the RC time constant on signal delay becomes greater.
One necessary approach to increasing signal transport speeds has been to reduce the dielectric constant of the dielectric insulating material used to form IMD layers thereby reducing the capacitance contribution of the IMD layer. Typical low-k (low dielectric constant) materials in use have included carbon doped silicon dioxide and other materials which tend to form a porous material thereby reducing the overall dielectric constant. Porous low-k materials have several drawbacks including enhanced absorption of chemical species by which may easily migrate throughout the IMD layer.
As feature sizes in anisotropic etching process have diminished, photolithographic patterning processes require activating light (radiation) of increasingly smaller wavelength. For 0.25 micron and below CMOS technology, deep ultraviolet (DUV) photoresists have become necessary to achieve the desired resolution. Typically DUV photoresists are activated with activating light source wavelengths of less than about 250 nm, for example, commonly used wavelengths include 193 nm and 248 nm. Many DUV photoresists are chemically amplified using a photoacid generator activated by the light source to make an exposed area soluble in the development process.
One problem affecting DUV photoresist processes is believed to be interference of residual nitrogen-containing species, for example amines, with the DUV photoresist. Residual nitrogen-containing contamination is one of the greater concerns in the use of metal nitride layers such as silicon oxynitride (e.g., SiON), which is commonly used as a bottom-anti-reflectance coating (BARC), also referred to as a dielectric anti-reflectance coating (DARC). Metal nitride layers, such as silicon oxynitride and silicon nitride are also frequently used as etching stop layers. The nitride layers are frequently formed by CVD processes using amine and amide containing precursors which tend to contaminate the near surface region of IMD layers. Low-k IMD layers typically having a high degree of porosity, facilitating absorption and transport of contaminating chemical species. For example, it is believed that nitrogen radicals, created during photolithographic patterning due to the presence of nitrogen containing species and absorbed into the IMD layer during metal nitride deposition, interfere with chemically amplified DUV photoresists by neutralizing a photogenerated acid catalyst which thereby renders the contaminated portion of the photoresist insoluble in the developer. As a result, residual photoresist remains on patterned feature edges, sidewalls, or floors of features, detrimentally affecting subsequent anisotropic etching profiles. During anisotropic etching of an overlying feature, for example a trench line opening overlying a via opening, residual photoresist remains or is redeposited on feature opening sidewalls. Consequently, necking, narrowing, or other undesirable etching profiles caused by polymeric residues remaining on feature sidewalls or floors following anisotropic etching, detrimentally affecting subsequent metal filling processes and leading to, for example, electrical open circuits or increased resistivity of interconnect features.
For example, referring to
FIG. 1
, is shown a dual damascene structure at a stage in manufacturing formed by a typical via-first dual damascene process, where the via opening
20
A is first formed followed by forming a trench line opening
20
B overlying and encompassing the via opening
20
A. The dual damascene structure including the via opening
20
A and the trench line opening
20
B are formed over an underlying conductive area
12
. The dual damascene structure is typically formed by at least two photolithographic patterning and reactive ion etching processes including first forming a via opening
20
A followed by a forming the trench line opening
20
B including anisotropically etching through a series of layers including for example a bottom anti-reflectance coating (BARC) layer
18
; a second dielectric insulating layer
16
B; a second etching stop layer
14
B; a first dielectric insulating layer
16
A; and finally, a first etching stop layer
14
A.
Chang Chih-Fu
Huang Yu-Chun
Nguyen Ha Tran
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
LandOfFree
Method for avoiding unetched polymer residue in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for avoiding unetched polymer residue in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for avoiding unetched polymer residue in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3146530