Semiconductor device manufacturing: process – Chemical etching – Having liquid and vapor etching steps
Reexamination Certificate
2006-08-15
2006-08-15
Smith, Bradley K. (Department: 2891)
Semiconductor device manufacturing: process
Chemical etching
Having liquid and vapor etching steps
C438S706000, C438S745000, C257SE21267
Reexamination Certificate
active
07091128
ABSTRACT:
A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.
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Ajmera Atul C.
Bryant Andres
Gilbert Percy V.
Gribelyuk Michael A.
Maciejewski Edward P.
Abate Esq. Joseph P.
Scully , Scott, Murphy & Presser, P.C.
Smith Bradley K.
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