Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-17
2003-02-11
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S628000
Reexamination Certificate
active
06518173
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to manufacturing high-density, multi-metal layer semiconductor devices exhibiting reliable electrical interconnections. More particularly, the present invention has particular applicability to multi-level semiconductor devices with design features of 0.25 &mgr;m and below, such as 0.18 &mgr;m, which devices employ copper or copper-based vias for electrically interconnecting metallization levels vertically spaced apart by dielectric material layers.
BACKGROUND OF THE INVENTION
The present invention relates to a method for performing metallization processing of particular utility in the manufacture of electrical and electronic devices, e.g., circuit boards and semiconductor integrated circuit devices, and is especially adapted for use in multi-level metallization processing utilizing “damascene” type “in-laid” technology and subtractive etching technology.
The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) semiconductor devices necessitate design features of about 0.25 &mgr;m and under, such as about 0.18 &mgr;m, increased transistor and circuit speeds, high reliability, and, increased manufacturing throughput. The reduction of design features to about 0.18 micron and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Semiconductor devices of the type contemplated herein typically comprise a substrate including a semiconductor wafer body, usually of doped monocrystalline silicon (Si) or, in some instances gallium arsenide (GaAs), and a plurality of sequentially formed interlayer dielectrics (“ILDs”) and electrically conductive patterns formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced-apart metallization layers or strata are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the ILD separating the layers or strata, while other conductive plugs filling contact area holes establish electrical contact with active device regions, such as source/drain regions of transistors formed in or on the semiconductor body. Conductive lines formed in groove- or trench-like openings in overlying ILDs extend substantially parallel to the semiconductor body. As schematically illustrated in
FIG. 1
in cross-sectional view, semiconductor devices of such type fabricated according to current technology may comprise five (5) or more layers or strata of such metallization in order to satisfy device geometry and microminiaturization requirements.
Electrically conductive films or layers of the type contemplated for use in e.g., “back-end” semiconductor manufacturing technology for fabricating devices having multi-level metallization patterns such as described supra, typically comprise a metal such as titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), chromium (Cr), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), copper (Cu), and their alloys. In use, each of the enumerated metals presents advantages as well as drawbacks. For example, Al is relatively inexpensive, exhibits low resistivity, and is relatively easy to etch. However, in addition to being difficult to deposit by lower cost, lower temperature, more rapid “wet” type technology such as electrodeposition, step coverage with Al is poor when the metallization features are scaled down to sub-micron size, resulting in decreased reliability of interconnections, high current densities at certain locations, and increased electromigration. In addition, certain low dielectric constant materials, e.g., polyimides, when employed as ILDs, create moisture/bias reliability problems when in contact with Al.
Copper (Cu) and Cu-based alloys are particularly attractive for use in large-scale integration (LSI), very large-scale integration (VLSI), and ultra large-scale integration (ULSI) semiconductor devices requiring multi-level metallization systems for “back-end” processing of the semiconductor wafers on which the devices are based. Cu- and Cu alloy-based metallization systems have very low resistivities, i.e., significantly lower than that of tungsten (W), and even lower than those of previously preferred systems utilizing aluminum (Al) and its alloys, as well as greater resistance to electromigration. Moreover, Cu and its alloys enjoy a considerable cost advantage over a number of the above-enumerated metals, notably silver (Ag) and gold (Au). Also, in contrast to Al and the refractory-type metals (e.g., Ti, Ta, and W), Cu and its alloys can be readily deposited at low temperatures in good quality, bright layer form by well-known “wet” plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with device manufacturing throughput requirements.
As indicated above, a commonly employed method for forming metallization patterns as are required for “back-end” metallization processing of semiconductor wafers employs “damascene” (or “in-laid”) technology. Generally, in such processing methodology, a recess (i.e., an opening) for forming, e.g., a via hole in an ILD for electrically connecting vertically separated metallization layers, or a groove or trench for a metallization line, is crated in the ILD by conventional photolithographic and etching techniques and then filled with a selected metal. Any excess metal overfilling the recess and/or extending over the surface of the ILD is then removed, as by chemical-mechanical polishing/planarization (“CMP”), wherein a moving pad is pressure-biased against the surface to be polished/planarized, with the interposition of a slurry containing abrasive particles (and other ingredients) therebetween.
A variant of the above-described technique, termed “dual damascene” processing (as, for example, disclosed in U.S. Pat. No. 5,635,423, the entire disclosure of which is incorporated herein by reference), involves the formation of a recess or opening in an ILD which comprises a narrower, lower contact or via hole section, in communication with a wider, upper groove or trench section, which dual function recess is then filled with a conductive material, typically a metal or metal alloy, to simultaneously form a conductive via plug in electrical contact with a conductive line.
Referring now to
FIG. 2
, schematically shown therein in simplified cross-sectional view, is a conventional damascene-type processing sequence employing low cost, high manufacturing throughput plating and CMP techniques for forming recessed, “back-end” metallization patterns (illustratively of Cu-based metallurgy but not limited thereto) in a semiconductor device formed in or on a semiconductor wafer substrate
1
. In a first step, the desired arrangement of conductors is defined as a pattern of recesses
2
such as via holes, grooves, trenches, etc., formed (as by conventonal photolithographic and etching techniques utilizing a fluorine-containing reactive plasma) in the surface
4
of a dielectric material (e.g., a silicon oxide, nitride, or oxynitride, or an organic polymeric material) deposited or otherwise formed over the semiconductor substrate
1
. In a second step, a layer
5
of Cu or Cu-based alloy is deposited by conventional plating techniques, e.g., electroless or electroplating techniques, to fill the recesses
2
. In order to ensure complete filling of the recesses, the Cu-containing layer
5
is deposited as a “blanket” (or “overburden”) layer of excess thickness t so as to overfill the recesses
2
and cover the upper surface
4
of the dielectric layer
3
. Next, the entire excess thickness t of the metal blanket or overburden layer
5
over the surface of the dielectric layer
3
is removed by a CMP process utilizing, e.g., an alumina (Al
2
O
3
Advanced Micro Devices , Inc.
Tsai Jey
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