Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-11
2004-09-21
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C324S754120
Reexamination Certificate
active
06795953
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to defect analysis on integrated circuit designs and in particular, to a method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design.
BACKGROUND OF THE INVENTION
Chemical mechanical polishing (CMP) is a widely adopted technique for global planarization during the fabrication of integrated circuits. Control of post-CMP topography variation is crucial, however, in meeting challenges like the ever decreasing depth-of-focus in photolithography and the ever increasing levels of interconnect due to routing complexity. Therefore, dummy interconnects are usefully placed in an integrated circuit design for leveling the integrated circuit topography for the CMP process.
Defect analysis, such as circuit area analysis, predicts failures of an integrated circuit that result from probabilistic defects. One problem with conventional defect analysis techniques is their general inability to avoid false failures attributable to dummy interconnects during defect analysis of an integrated circuit design. In particular, such defect analysis is generally unable to distinguish the difference between a true failure resulting from a simulated defect impinging upon a current carrying interconnect and a false failure resulting from a simulated defect impinging upon a dummy interconnect. The second case is referred to as being a “false failure”, because such occurrence has no significant effect on the functionality or performance of the integrated circuit design. This deficiency may thus result in overly conservative design and unnecessary testing for false failures, both of which add unwarranted cost to the manufacture of the integrated circuit.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is a method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design.
This and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is a method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design, comprising: providing a target layer generated by including electrical current carrying interconnects of an integrated circuit design, but not including dummy interconnects of the integrated circuit design; and performing defect analysis of the integrated circuit design using the target layer.
Another aspect is a method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design, comprising: storing interconnect polygon information for an integrated circuit design into a dummy polygons layer; copying the interconnect polygon information from the dummy polygons layer to a target layer, except for dummy interconnect polygon information; and performing defect analysis of the integrated circuit design using the target layer instead of the dummy polygons layer.
Still another aspect is a method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design, comprising: retrieving conductivity layers information for an integrated circuit design from a GDSII formatted file; defining a dummy polygons layer and a target layer; restoring interconnect polygons from the conductivity layers information into the dummy polygons layer; copying the interconnect polygons from the dummy polygons layer to the target layer, except for dummy interconnect polygons; and performing defect analysis of the integrated circuit design using the target layer.
Additional objects, features and advantages of the various aspects of the invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.
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D. Woodie, “Chemical Mechanical Polishing Primer”, [Internet], http://www.nnf.cornell.edu/equipment/CMPPrimer.html, 14 pages printed May 18, 2002 (no date).
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Bakarian Sergei
Segal Julie
HPL Technologies, Inc.
Sierra Patent Group Ltd.
Thompson A. M.
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