Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-06-06
2006-06-06
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07058916
ABSTRACT:
In a method of automatically sizing and biasing a circuit, a database is provided including a plurality of records related to cells that can be utilized to form an integrated circuit. A cell parameter of a cell for a circuit is selected and compared to cell parameters residing in the records stored in the database. One record in the database is selected based upon this comparison and a performance characteristic of the circuit is determined from this record.
REFERENCES:
patent: 5513119 (1996-04-01), Moore et al.
patent: 5757655 (1998-05-01), Shih et al.
patent: 6131182 (2000-10-01), Beakes et al.
patent: 6490715 (2002-12-01), Moriwaki et al.
patent: 6529913 (2003-03-01), Doig et al.
patent: 6539533 (2003-03-01), Brown et al.
patent: 2002/0175713 (2002-11-01), Knowles
Carley L. Richard
Gadient Anthony J.
Phelps Rodney
Rohrer Ronald A.
Rutenbar Rob A.
Cadence Design Systems Inc.
Morrison & Foerster / LLP
Rossoshek Helen
Thompson A. M.
LandOfFree
Method for automatically sizing and biasing circuits by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for automatically sizing and biasing circuits by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for automatically sizing and biasing circuits by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3617960