Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1997-10-20
2001-09-18
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S015000, C703S016000, C716S030000
Reexamination Certificate
active
06292765
ABSTRACT:
CROSS-REFERENCE TO MICROFICHE APPENDICES
Microfiche appendices 1-58 (of 89 sheets and 4,945 frames) that are attached hereto contain source code in C language for programming a computer, are a part of the present disclosure, and are incorporated by reference herein in their entirety.
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office patent files or records, but otherwise reserves all copyright rights whatsoever.
FIELD OF THE INVENTION
The present invention relates generally to a method implemented by a programmed computer for verifying the functionality of digital circuits during development and testing. More specifically, the invention relates to an automated method for searching for functional defects in a description of a circuit-under-verification.
BACKGROUND OF THE INVENTION
Modern digital electronic circuits are typically designed at the register-transfer (RTL) level in hardware description languages such as Verilog (see “The Verilog Hardware Description Language”, Third Edition, Don E. Thomas and Philip R. Moorby, Kluwer Academic Publishers, 1996) or VHDL (see “A Guide to VHDL”, Stanley Mazor and Patricia Langstraat, Kluwer Academic Publishers, 1992). A circuit description in such a hardware description language can be used to generate logic circuit elements as described, for example, in U.S. Pat. No. 5,661,661 granted to Gregory and Segal.
Such hardware description languages facilitate extensive simulation and emulation of the described circuit using commercially available products such as Verilog-XL available from Cadence Design Systems, San Jose, Calif., QuickHDL available from Mentor Graphics, Wilsonville, Oreg., Gemini CSX available from IKOS Systems, Cupertino, Calif., and System Realizer available from Quickturn Design Systems, Mountain View, Calif. These hardware description languages also facilitate automatic synthesis of ASICs (see “HDL Chip Design”, by Douglas J. Smith, Doone Publications, 1996; “Logic Synthesis Using Synopsys”, Pran Kurup and Taher Abbasi, Kluwer Academic Publishers, 1997) using commercially available products such as Design Analyzer and Design Compiler, available from Synopsys, Mountain View, Calif.
As described in “Architecture Validation for Processors”, by Richard C. Ho, C. Han Yang, Mark A. Horowitz and David L. Dill, Proceedings 22
nd
Annual International Symposium on Computer Architecture, pp. 404-413, June 1995, “modern high-performance microprocessors are extremely complex machines which require substantial validation effort to ensure functional correctness prior to tapeout” (see page 404). As further described in “Validation Coverage Analysis for Complex Digital Designs” by Richard C. Ho and Mark A. Horowitz, Proceedings 1996 IEEE/ACM International Conference on Computer-Aided Design, pp. 146-151, November 1996, “the functional validation of state-of-the-art digital design is usually performed by simulation of a register-transfer-level model” (see page 146).
It is well known to monitor the operation of a simulation test by using, for example, “snoopers” generated manually as described at page 463, column 2, in “Hardware/Software Co-Design of the Stanford FLASH Multiprocessor”, by Mark Heinrich, David Ofelt, Mark A. Horowitz, and John Hennessy, Proceedings of the IEEE, Vol 85, No. 3, pp. 455-466, March 1997, and in “Functional Verification Methodology for the PowerPC 604 Microprocessor”, by James Monaco, David Holloway and Rajesh Raina, Proceedings 33
rd
IEEE Design Automation Conference, pp. 319-324, June 1996.
Another prior art system monitors the operation of a simulation test by using a “golden model” that is “written without reference to the RTL” and is “co-simulated using the same set of test vectors”, as described by Chian-Min Richard Ho, in “Validation Tools for Complex Digital Designs”, Ph.D. Dissertation, Stanford University Computer Science Department, November 1996 (at page 6, Section 2.1).
Prior-art products (for example, see the “Purify” product from Pure Atria, Sunnyvale, Calif., and the “Insure++” product from ParaSoft, Monrovia, Calif.) exist for testing software programs that may be written, for example in the programming language “C” described by Brian W. Kernighan and Dennis M. Ritchie in the book “The C Programming Language”, Second Edition, PTR Prentice Hall, 1988. See “Purify User's Guide, Version 4.0”, Pure Atria Corporation, 1996, and “Insure++ Automatic Runtime Debugger User's Guide”, ParaSoft Corporation, 1996.
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Singer, S.; Vanetsky, L.;“Next Generation Test Generator (NGTG) for Digital Circuits”, Proceedings of IEEE Autotestcon, pp. 105-112, Sep. 1997.*
Liang et al., “Identifying Invalid States for Sequential Circuit Test Generation”, IEEE Trans. on Computer-Aided Design of Int. Circuits and Systems, vol. 16, Issue 9, pp. 1025-1033, Sep. 1997.*
Liang et al., “Identifying Invalid States for Sequential Circuit Test Generation”, Proc. of the Fifth Asian Test Symposium 1996, pp. 10-15, Nov. 1996.*
Camurati et al., “Efficient Verification of Sequential Circtuis on a Paralle System”, Proc. Third European Conference on Design Automation, pp. 64-68, Mar. 1992.
Dill David Lansing
Estrada Paul II
Giomi Jean-Charles
Ho Chian-Min Richard
Lin Jing Chyuarn
O-In Design Automation
Sergent Douglas W.
Skjerven Morrill & MacPherson LLP
Suryadevara Omkar K.
Teska Kevin J.
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