Method for automatically modifying integrated circuit layout

Details Method for automatically modifying integrated circuit layout Method for automatically modifying integrated circuit layout

2006-08-29

2009-02-24

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07496862

ABSTRACT:
This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (M1s) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.

REFERENCES:
patent: 5625568 (1997-04-01), Edwards et al.
patent: 2007/0113216 (2007-05-01), Zhang

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