Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-11-08
2005-11-08
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06964030
ABSTRACT:
A method for translating mask tooling information comprises the steps of: receiving a plurality of input mask tooling forms for fabricating a wafer, at least two of the plurality of input masking tool forms having respectively different sequences of layers; forming a template having a sequence of layers formed by the union of the different sequences of layers; and translating information from each of the input mask tooling forms to fit the template.
REFERENCES:
patent: 5784292 (1998-07-01), Kumar
patent: 6643841 (2003-11-01), Chang et al.
patent: 2002/0093514 (2002-07-01), Edwards et al.
patent: 2004/0158344 (2004-08-01), Inobe et al.
Feng Shu-Ling
Hong Hsin-Ming
Tsao Piao-Chuo
Tseng Yi-Hong
Duane Morris LLP
Koffs Steven E.
Lin Sun James
Siek Vuthe
Taiwan Semiconductor Manufacturing Co. Ltd.
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