Method for automatic clock gating to save power

Details Method for automatic clock gating to save power Method for automatic clock gating to save power

2011-04-19

2011-04-19

Levin, Naum (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Optimization

C716S119000, C716S136000, C713S500000

Reexamination Certificate

active

07930673

ABSTRACT:
A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.

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