Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-07-30
2003-07-01
Tran, Khai (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
06587533
ABSTRACT:
FIELD OF THE INVENTION
The object of the invention is a method according to the preamble of claim 1 for attenuating transients caused by the transmission system's justification events in a desynchroniser. The invention also relates to a circuit arrangement for realising the method.
BACKGROUND OF THE INVENTION
In order to standardise and improve digital communication by wire the synchronous digital hierarchy was developed in order to replace the present, the so called plesiochronic system. As a concept the synchronous digital hierarchy means firstly that all nodes in a digital communications network are basically synchronised to the same clock, and secondly that the transmitted data is arranged into frames, which are defined on several levels according to a hierarchic order. The essential definitions regarding the operation of the arrangement are contained in the ITU specifications G.703, G.70X (Draft) and G.781-G.784. The transmitted data frames are called STM-N frames, where STM is an abbreviation for Synchronous Transport Module and N refers to the number of the hierarchy level. The frames of the lowest hierarchy level are STM-1 frames and they are used for instance in the present 2, 8, 34 and 140 Mbit/s PCM systems. for packing the transmitted data. The transmission rate of the STM-1 frames or the so called basic rate in the SDH system is 155,520 Mbit/s. On the higher hierarchy levels the transmission rates are multiples of this lowest level rate.
The structure of an STM-1 frame is illustrated in FIG.
13
. It can be represented by a matrix having 9 rows and 270×N columns. The matrix elements are bytes, so that one frame contains 2430×N bytes. The 9×N first columns of the matrix comprise header and address information, so that the rows 1 to 3 and 5 to 9 of these columns belong to the so called section overhead (SOH) and the row 4 comprises the pointers of so called administrative units (AU). The rest of the STM-1 transmission frame comprises one or more administrative units. The example shows an AU unit AU-4 of the highest level, in which, correspondingly, is placed a highest level virtual container VC-4 in which for instance a 139264 kbit/s plesiochronic information signal can be directly mapped. Alternatively the transmission frame STM-1 can contain several lower level AU units, and into each of these unit is placed a virtual container VC of the corresponding lower level. In
FIG. 13
the VC-4 on the other hand is formed by a path overhead POH of one byte and an information bit group of 240 bytes, whereby a particular control byte is placed at the beginning of each. Some of these control bytes are used i.a. to perform the interface justification in connection with the mapping, when the rate of the mapped information signal is slightly offset from its nominal value. The mapping of the information signal into the transmission frame STM-1 is described for instance in the patent applications AU-B-34689/89 and FI-914746.
A tributary unit (TU) forms the connection between a higher and a lower hierarchy level. It comprises a payload, or the VC frame, and a pointer, which indicates where the payload is positioned in the TU frame. The administrative unit (AU) and the tributary unit (TU) differ in that the AU is an assembly which can be cross connected in the network and transmitted between different STM signals, but the TU is an internal unit of a particular frame, and the TU can not be transmitted between different STM-1 signals without an administrative unit of a higher level. One or more tributary units (TU) having a fixed position in a higher level VC frame form a tributary unit group (TUG), which is formed by multiplexing the TU's. A group can be formed by tributary units of different sizes.
A container (C) is the synchronous payload of each VC. It comprises a payload signal whose frequency can be justified when required so that will be synchronous with the corresponding STM-1 signal. In the future a container can also be a broadband signal.
Each byte in the AU-4 unit has a position number. The above mentioned AU pointer contains the address of the position of the first byte of the VC-4 container in the AU4 unit. With the aid of the pointers it is also possible to perform so called positive or negative pointer justification in different points of the SDH network. If a network node operating at a certain clock frequency receives from the outside a VC having a clock frequency which is higher than the above mentioned the result will be that the data buffer is filled. Then a so called negative justification must be performed. Then one byte from the received VC container is moved to the header side and the number of the pointer is correspondingly reduced by one.
On the other hand, if a received VC has a lower rate than the clock rate of the node, then the data buffer tends to empty, and a positive justification must be made, where a fill byte is added to the VC container, and the pointer value is increased by one.
Both the bit justification used in mapping (interface justification) and the above mentioned pointer justification generate phase jitter, which the desynchroniser should be able to equalise at the exit from the SDH network. Phase jitter and its equalisation is described for instance in the lecture “Simulation results and field trial experience of justification jitter” by Ralph Urbansky, 6th World Telecommunication Forum, Geneva, Oct. 10-15, 1991, International Telecommunication Union, Part 2, Vol III, p. 45-49.
Two principles for filtering jitter and fluctuations have been adopted in SDH desynchronisers. The simpler of these is based on a phase-locked loop (PLL) and it is often called a “narrow bandwidth desynchroniser”, because the filtering of even the worst pointer justification events (PJE) is made only with this phase-locked loop. The more complex solution is called a “bit-leaking desynchroniser”, because PJE phase hits are prejustified in a jitter spreading process (=bit spreading) before the actual PLL loop. In a bit-leaking desynchroniser the bandwidth of the PLL loop is about one decade wider than the bandwidth of the PLL loop in a narrow bandwidth desynchroniser.
For this purpose the known desynchronisers comprise a data buffer, to which is connected an analogue phase-locked loop, with which the data buffer read clock is phase-locked to the read clock. As the phase-locked loop acts as a low-pass filter it removes the jitter, except components at the lowest frequencies. For instance the SDH pointer justification generates typically much stronger jitter components than the bit stuffing, because single phase hits in the pointer justification are for instance 8 or 24 frame unit intervals UI, and because the frequency of the phase hits caused by pointer justification can represent a very low frequency, which is poorly filtered in the phase-locked loop of the desynchroniser. A sufficient attenuation of the pointer jitter with the aid filtering would require that the bandwidth of the loop is designed to be very narrow (the absolute value depends on the rate of the interface in question). The
FIGS. 14 and 15
show how the jitter peaks of two pointer phase hits of 24 UI (measured at the desynchroniser output by a measuring filter defined by ITU) can be reduced with strong filtering to an acceptable peak level of about 0.2 UI, when the bandwidth of the phase-locked loop at the rate 140 Mbit/s is about 2 Hz. However, no pointer justifications are required in normal operating conditions, and only the interface bit justifications are active. Thus the dimensioning of the phase-locked loops of the desynchronisers on the basis of pointer phase hits is un-reasonable, because regarding the bit stuffing the bandwidth of the phase-locked loop could be even ten-fold. Then the locking of the loop would also be more reliable and the locking time would be substantially shorter.
A known solution to this problem is the so called bit leaking, where the phase hits caused by the pointer are removed in a non-linear process (in the time domain), which tre
Nokia Corporation
Squire Sanders & Dempsey L.L.P.
Tran Khai
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